6713 memory partition problems

da cheng said:

IVECS:   org=0h, len=0x220

IRAM  :   org=0x00000320,  len=0x0000ffd8

SDRAM: org=0x80000000, len=0x01000000

flash: org=0x90000000,   len=0x00020000,

1) I know the last three are internal ram, external ram, and flash, but what is the first partition? Why do we use size (0x220)?

IVECS is for the Interrupt Service Table (aka Interrupt Vectors).  There are 16 vectors for the DSP, and each vector is allocated 32 bytes of memory.

16 Vectors * 32 Bytes = 512 Bytes = 0x200 Bytes.

You can learn more about this in the DSP reference guide: http://www.ti.com/litv/pdf/spru733a

da cheng said:

2) length of the internal ram is 0x0000ffd8, but  in the data sheet, I only found the following information:

On-Chip L1/SRAM: 8 KB

On-Chip L2/SRAM: 64 KB Cache/192 KB SRAM 

I don't find any information about internal memory, let alone the size(ffd8)

The IVECS and IRAM sections are both located inside the L2 RAM memory space.  You can refer to the datasheet Memory Map Summary for the address space table.  The .cmd file does not need to allocate the entire available memory space.

da cheng said:

3)when defining the org(start address), why do we choose org=0x80000000,org=0x90000000?

I know the length is due the 16MB external SDRAM, and 512k flash.

These are the base addresses for the appropriate memory spaces.  Again, you can refer to the datasheet Memory Map Summary.

da cheng said:

4) In my opinion, all the above are programming memory, right? Then where should I define data memory?

Only L1 memory is split between program and data memory.  From L2 and beyond (away from DSP), the memory is unified between program and data.

Hello Sir,

I have read this guide before I posted my questions,seems there is no memory mapping information.

Is there any other user's guides that I can reference?

From your reply, I am still confused with the configuration of "org" and the setting up data memory space.

1)If possible, can you give me a brief explanation of ,for example, why choose org =0x80000000? Alternatively, we can set each memory partition immediately after the previous one.

2)also, for some application, I may need the read data from outside, then I need to define a data memory space. Then what should I do?

regards,

-da

For the 4) question, do you mean that the 6713 dsp is implementing a von neumann architecture?

Several years ago, when I took the DSP course at university, I think the data memory is separate from program, it is a harvard architecture, which has a better performance(dealing with data and instruction at the same time).

Is there a architecture transfer from harvard to von neumann in DSP family?

regards,

-da

Thank you, very clear.

Is the unified memory controller a new feature in C67x ?

If not, can you tell me when did TI start unifying data and program memory?

A harvard architecture(data and program treated separately) should be faster as data operation and instruction can be done in the same cycle.

Why did TI unify the two memory divisions.

regards,

-da

The TI C6x  DSP core (C62, C64, C64x+, C67 and C674x) is RISC-oriented and its internal memory architecture is still based on Harvard architecture - i.e. separate program and data buses with load and stores to a register file.  As processor core speed far outpaced external memory speed, a 2-level memory including cache architecture is introduced to keep the core ... fully fed. The DSP core still accesses L1 memory as Harvard, i.e. there are L1P (level 1 program) and L1D (level 1 data) memories, but program and data spaces are merged (unified) at level 2 (L2) memory. This change started with the C6211 and continues until today.

For a perspective on the evolution of the C6000 VLIW DSP core memory architecture, consult the TMS320C6000 Technical Brief (SPRU197), and the TMS320c64x Technical Overview (SPRU395).