This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSMC System Master Port stalls the MSMC Emif Master Port

Other Parts Discussed in Thread: TCI6638K2K

Hello there dear TI Engineers,

 

We have a problem with the ARM memory accesses in the TCI6638K2K SoC. We suspect that accessing the MSMC System Master Port stalls the MSMC EMIF Master Port accesses.

I don’t have extensive debug utilities to directly address the stalls. So let me explain the situation:

 

Test 1.a:

We have four ARM cores. Core 0 does various NVM accesses (MSMC System Master Port->Teranet->EMIF16), while Core 1&2&3 does several jobs with only DDR accesses.

We monitor the cores using the ARM Performance Monitor Unit. In this test, we see the execution time of the jobs in Core 1&2&3 have very high measurement peaks (for example 10 to 20 times of the average time).

 

Test 1.b:

We run the same test, except this time we do not access to NVM (hence no access to the MSMC System Master Port).

We don’t measure any of the peaks which occurred in the previous test.

 

Test 2.a:

So we disable the NVM accesses in this second set of tests. Instead, we access to the SoC Configuration Bus to simply read the timer register (which happens through the MSMC System Master Port according to the block diagrams).

Again we measure some peaks in our measurements (but not as high as compared to the first test).

 

Test 2.b:

We disable the access to the timer and peaks are gone.

We repeat these tests many times and always the results are similar.

 

According to this results, we may normally conclude the MSMC System Master Port accesses stalls the MSMC EMIF Master Port accesses.

My question is, naturally, is this situation valid in the SoC and is there a way to prevent these stalls? Maybe the stalls are normal (I don't know) but why do they take thousands of cycles? My point is, I am looking for a direction from an experienced hand to better understand and solve (or mitigate) the problem.

We have high time critical requirements and these stalls gives us a really bad headache (in terms of performance and deterministic measurements). I will be very happy if you can help me in this situation.

 

Thank you,

Erman

Block Diagrams:

Note: About one year ago, I mentioned a similar problem in this post: https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/516035


But this post is a more detailed one and includes MSMC Master System Port accesses which points me to a rather SoC problem...