TDA2HG: PCI express root complex

Deepa Gopinath65

Part Number: TDA2HG

Hi,

1. What is the difference between root port and virtual root port in PCIe root complex?

2. What is the size of configurable address space of PCIe root complex in Tda2xx Platform?

3. In PCIE Spec, it is mentioned that PCIE Address space is a virtual adrress. Do we have assigned any of the system address to this PCIE address space ?.

4. In Starterware PCIE write_loopback example, data is transferred from RC device to EP device and vice versa.

Can you please explain how the data will be transferred to EP device when we write data to outbound region - 0x25000000 ?

Thanks in Advance!!

Regards,
Deepa

over 7 years ago

0 Yordan Kamenov over 7 years ago

TI__Mastermind 42515 points

Hi Deepa,

I have forwarded your question to a PCIe expert for comment.

Regards,
Yordan

0 B.C. over 7 years ago

TI__Genius 16956 points

1. I'm not familiar with virtual root ports.

2. 4GB inbound, 256MB outbound.

3. Mapping from PCIe address space to SoC address space is completely configurable by software using the Address Translation Unit (ATU)

4. The Address Translation Unit (ATU) is programmed by software to translate accesses to the PCIe outbound window into the desired PCIe address space.

See more details in the TRM section "PCIe Controller Ports on L3_MAIN Interconnect".

0 Deepa Gopinath65 over 7 years ago in reply to B.C.

Prodigy 70 points

Hi,

Thanks for the details.
Can you please explain with an example how SOC RAM is mapped to PCIe address space using ATU?
How outbound and inbound region is related to this mapping?

Can I connect multiple PCIe end points to J6 PCIe controller with out using switch?

Thanks in Advance

Regards,
Deepa

0 B.C. over 7 years ago in reply to Deepa Gopinath65

TI__Genius 16956 points

Please see TRM sections "PCIe Controller Address Spaces and Address Translation" and "PCIe Traffic Requesting and Responding" for details on configuring the address translation for inbound and outbound transactions.

Also, please reference the TDA2xx Starterware and Processor SDK PCIe examples for code examples.

J6 can attach to one PCIe endpoint per PCIe controller without a switch.

0 Deepa Gopinath65 over 7 years ago in reply to B.C.

Prodigy 70 points

Hi,

Thanks for the reply.
I have gone through the J6 TRM and Starterware example code base. But unable to understand these details
Can you please explain with an example how SOC RAM is mapped to PCIe address space using ATU?
How outbound and inbound region is related to this mapping?
It will be grateful if someone explains me with an example

Thanks in Advance

Regards,
Deepa

0 B.C. over 7 years ago in reply to Deepa Gopinath65

TI__Genius 16956 points

Here is an example Inbound Address Translation Configuration (Address Match Mode) that translates access from PCIe Address 0x1100_0000 to OCMC_RAM1 address 0x4030_000:

Step	Description	Register	Value	Comment
1	Write the INDEX register to select desired region to program	PCIECTRL_PL_IATU_INDEX	0x8000_0000	Inbound Region 0
2	Write the BASE registers with the desired PCIe Base Address for the region	PCIECTRL_PL_IATU_REG_LOWER_BASE PCIECTRL_PL_IATU_REG_UPPER_BASE	0x1100_0000 0x0	PCIe Address Space
3	Write the LIMIT register with the desired PCIe window size for the region	PCIECTRL_PL_IATU_REG_LIMIT	0x0000_FFFF	PCIe Address Space
4	Write the TARGET registers with the desired SoC address	PCIECTRL_PL_IATU_REG_LOWER_TARGET PCIECTRL_PL_IATU_REG_UPPER_TARGET	0x4030_0000 0x0	Corresponds to OCMC_RAM1
5	Configure the region as desired	PCIECTRL_PL_IATU_REG_CTRL_1	0x0	Default settings
6	Enable the region	PCIECTRL_PL_IATU_REG_CTRL_2	0x8000_0000	Address Match Mode
7	Repeat 1-6 for additional regions

0 Deepa Gopinath65 over 7 years ago in reply to B.C.

Prodigy 70 points

Hi,

Thanks for the reply. This explains me about Inbound Configuration for one end of communication.
During Address match mode, BAR configuration is not required? How the Address match mode works ?
Can you please explain the same for Outbound Configuration for other end of communication?

Thanks in Advance!!

Regards,
Deepa

0 B.C. over 7 years ago in reply to Deepa Gopinath65

TI__Genius 16956 points

Deepa,

Here's an example outbound configuration:

Step	Description	Register	Value	Comment
1	Write the INDEX register to select desired region to program	PCIECTRL_PL_IATU_INDEX	0x0	Outbound Region 0
2	Write the BASE registers with the desired SoC base address offset within the PCIe_SSx Configuration space.	PCIECTRL_PL_IATU_REG_LOWER_BASE PCIECTRL_PL_IATU_REG_UPPER_BASE	0x0100 0000 0x0	Corresponds to SoC address 0x2100_0000 (Assuming PCIE_SS1)
3	Write the LIMIT register with the desired window size for the region.	PCIECTRL_PL_IATU_REG_LIMIT	0x000 FFFF	Corresponds to SoC address 0x2200_0000 (Assuming PCIE_SS1)
4	Write the TARGET registers with the desired PCIe address	PCIECTRL_PL_IATU_REG_LOWER_TARGET PCIECTRL_PL_IATU_REG_UPPER_TARGET	0x1100 0000 0x0	PCIe Address Space
5	Configure the region as desired	PCIECTRL_PL_IATU_REG_CTRL_1	0x0	Default settings
6	Enable the region	PCIECTRL_PL_IATU_REG_CTRL_2	0x8000’0000	Address Match Mode
7	Repeat 1-6 for additional regions

As a Root Complex, Address Match mode is the standard method of address translation. It simply translates directly between the SoC address space and PCIe address space.

Regards,

Brad

0 Deepa Gopinath65 over 7 years ago in reply to B.C.

Prodigy 70 points

Hi Brad,

Thanks for the details.

1. Can you please explain the difference between Address match mode and BAR Configuration Mode?

2. In Starterware example, While testing write_loopback PCIe example, we connect both the J6 EVM via PCIe Link. One J6 EVM is configured for RC and other is for Endpoint. RC is connected to Bus-0 by default and EP will be connected to Bus-1 after Enumeration. PCIe Address space will be determined by Bus Number, Device number, Function Number and Cfg register address.
In ep_write_loopback_app_main.c file, OUTBOUND_PCIE_ADDRESS is 0xB0000000U and INBOUND_PCIE_ADDRESS is 0xA0000000U where as in rc_write_loopback_app_main.c file OUTBOUND_PCIE_ADDRESS is 0xA0000000U and INBOUND_PCIE_ADDRESS is 0xB0000000U. In both cases, bus number is defined as '0'.
Can you please explain how the outbound and Inbound PCIe address space is determined in case of RC and EP STW Example?

Thanks in Advance!!

Regards,
Deepa

0 B.C. over 7 years ago in reply to Deepa Gopinath65

TI__Genius 16956 points

Deepa,

1. In BAR Match Mode, the BASE and LIMIT registers are not used. Instead, the address defined by the selected BAR is used.

2. In PCIe, the RC and all attached EPs use a common/unified PCIe address space. Therefore in Starterware, the outbound address of the RC is configured to be the same as the inbound address of the EP, and vice versa.

0 Deepa Gopinath65 over 7 years ago in reply to B.C.

Prodigy 70 points

Hi Brad,

Thanks for the Details.
1. Can you please point to an example which uses BAR Match Mode ?
2. Yes I can understand that the outbound address of the RC is configured to be the same as the inbound address of the EP, and vice versa.
I want to know How the OUTBOUND_PCIE_ADDRESS (0xB0000000U) and InBOUND_PCIE_ADDRESS (0xB0000000U) is determined in starterware example? Based on what parameters this PCIe address is determined?

Thanks & Regards,
Deepa

0 B.C. over 7 years ago in reply to Deepa Gopinath65

TI__Genius 16956 points

Deepa,

1. BAR Match mode follows the same basic sequence, except:

- The BASE and LIMIT registers do not need to be programmed

- BAR Match mode, along with the the desired BAR NUMBER should be programmed in the PCIECTRL_PL_IATU_REG_CTRL_2 register

All accesses to the BAR will be remapped to the programmed TARGET address.

2. The outbound and inbound addresses were picked arbitrarily. They can be any addresses in the PCIe address space.

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TDA2HG: PCI express root complex