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AM3715: Enabling ECC for L2 cache

Zane Tarumoto
Prodigy 50 points
Part Number: AM3715


So my software engineer was attempting to enable ECC fro l2 Cache and was unable to using this code snippet for an AM3715:

MRC p15, 1, <Rd>, c9, c0, 2 ; Read L2 Cache Auxiliary Control Register

ORR <Rd>, <Rd>, #0x0020_0000; Set parity/ECC enable

MCR p15, 1, <Rd>, c9, c0, 2 ; Write L2 Cache Auxiliary Control Register

MRC p15, 1, <Rd>, c9, c0, 2 ; Read L2 Cache Auxiliary Control Register

TST <Rd>, #0x0020_0000 ; Test for parity/ECC enable

BEQ no_parity_ram_setup

parity_ram_setup:

;<do parity RAM setup>

B done_parity_RAM_setup

no_parity_ram_setup:

;<do no parity/ECC RAM setup>

done_parity_RAM_setup:

;<continue>

He stated that the all indications show that the processor does not support this function.  The cortex a8 shows this is the step to enable it and to verify that it was enabled, but he stated that it does not enable.  Does this processor support ECC and if so what is the code I need to implement that will enable the bit.  Thank you!

  • 0
    TI__Guru**** 393215 points
    The factory team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 90235 points
    Zane, the L2 Cache Auxiliary Control Register has to be written in a secure mode. The AM37x provides a monitor API to perform CP15 writes in secure mode. Please check out section 26.4.1 "Booting Overview" for a description of these services.

    Regards,
    James
  • 0 in reply to JJD
    Prodigy 50 points
    So They have attempted this:
    mrc p15, 1, r0, c9, c0, 2 /* Read L2 Cache auxiliary control register */
    orr r0, r0, #0x10000000 /* Set to ECC instead of parity */
    orr r0, r0, #0x00200000 /* Set ECC enable bits */
    ldr r12,=2 /* Setup the write to the L2 Cache auxiliary control register */
    dsb
    isb
    dmb
    smc #1 /* Write the L2 cache auxiliary control register */

    which I believe matches the section referenced. After executing this code we read the L2 cache auxiliary control register and bit 21 is not set but bit 28 is. So we can write to this register, but for some reason bit 21 is not able to be written.
  • 0 in reply to Zane Tarumoto
    TI__Guru* 90235 points

    Hi Zane, not sure what could be going wrong.  Can you ensure you don't have the L2 cache enabled when you try to enable the ECC.  I found the following sequence in the ARM TRM

    To enable the L2 cache following a reset or to change the settings of the L2 Cache

    Auxiliary Control Register, you must use the following sequence:

    1. Complete the processor reset sequence or disable the L2 cache.

    2. Program the L2 Cache Auxiliary Control Register. See c9, L2 Cache Auxiliary

    Control Register on page 3-124 for details.

    Note

    If you have configured the processor to support parity or ECC memory, you must

    enable those features before you can program the C bit.

    3. Program the Auxiliary Control Register to set the L2EN bit to 1. See c1, Auxiliary

    Control Register on page 3-61 for details.

    4. Program the C bit in the CP15 Control Register c1. See c1, Control Register on

    page 3-58 for details.

     

    Regards,

    James