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DRA72XEVM: maximum address range for a single J6 QSPI

BillyO
Genius 17555 points

Part Number: DRA72XEVM

Hi team,

 

We have a customer that is looking to confirm the maximum address range for a single J6 QSPI Chip select ( i.e 64Mbytes, 128Mbytes,...).

 

Thanks in advance,

Billy

 

  • 0
    TI__Mastermind 25170 points
    Hi Billy,
    J6 has 64 Mbytes per chip select address space:

    QSPI_ADDRSP1 0x5C00 0000 0x5FFF FFFF 64MiB QSPI CS0/CS1/CS2/CS3 space (Maddrspace 1)

    Chip-selects are switched through the CTRL_CORE_CONTROL_IO_2[10:8] QSPI_MEMMAPPED_CS register field.

    Regards,
    Stan
  • 0 in reply to Stanislav Stilyanov
    Prodigy 100 points
    Hi Stan,

    Much appreciate your feedback.

    Have two follow questions concerning the J6 QSPI:

    1. Is there any means to configure the J6 to map multiple chip select together so a single Q SPI Chip Select can access 128Mbytes or 256Mbytes?
    i.e. 1Gbit(128MBytes) & 2Gbit(256MBytes) are standard QSPI offerrings

    2. Is my interpretation correct that the J6 has a single QSPI port; is there additional pin muxing possibilities to enable 2 QSPI ports.

    Thanks and have a good one,

    Ken Perdue
    MXIC Auto FAE
  • 0 in reply to Ken Perdue
    TI__Mastermind 25170 points

    Hi Ken,

    1. In memory-mapped mode, the max configuration could be 4 memory chips x 64 Mbytes each. I think it could be possible to access more than 64MB in serial mode (not memory-mapped) but it is far more slower and I don't know if it is supported by the driver.

    2. There is only one instance of the QSPI controller on J6. QSPI was added as an alternative method to boot in systems with limited space. Other methods include eMMC, NAND, NOR, and SATA. (and SD cards)

    You can learn more about QSPI controller in the J6 TRM document. Linux driver overview can be found here:

    Best regards,

    Stan