Tool/software: Linux
Hello,
I am trying to set up a driver to use eqep0 and I am noticing that CM_PER_EPWMSS0_CLKCTRL is not being enabled. I have the following device tree setup for these modules. am33xx.dtsi matches the sdk except for these changes. I believe ti,hwmods = "epwmss0" should be enabling this gate, but it seems like it is not. Am I missing some setting? I have verified that my "my-eqep" driver is starting and I don't see any complaints in the log about hwmods not starting epwmss0.
am33xx.dtsi
ocp {
epwmss0: epwmss@48300000 {
compatible = "ti,am33xx-pwmss";
reg = <0x48300000 0x10>;
ti,hwmods = "epwmss0";
#address-cells = <1>;
#size-cells = <1>;
status = "disabled";
ranges = <0x48300100 0x48300100 0x80 /* ECAP */
0x48300180 0x48300180 0x80 /* EQEP */
0x48300200 0x48300200 0x80>; /* EHRPWM */
ecap0: ecap@48300100 {
compatible = "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
interrupts = <31>;
interrupt-names = "ecap0";
status = "disabled";
};
ehrpwm0: pwm@48300200 {
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x80>;
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
eqep0: eqep@0x48300180 {
compatible = "my-eqep";
reg = <0x48300180 0x80>;
clocks = <&eqep0_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
interrupt-parent = <&intc>;
interrupts = <79>;
status = "disabled";
};
};
am335x-mine.dts
&eqep0 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&eqep0_default>;
pinctrl-1 = <&eqep0_sleep>;
};
&epwmss0 {
status = "okay";
};
&ehrpwm0 {
status = "okay";
};
&am33xx_pinmux {
eqep0_default: eqep0_default {
pinctrl-single,pins = <
/* Quadrature Encoder 0 */
0x1a0 (PIN_INPUT | MUX_MODE1) /* (B12) mcasp0_aclkr.eQEP0A_in */
0x1a4 (PIN_INPUT | MUX_MODE1) /* (C13) mcasp0_fsr.eQEP0B_in */
0x1a8 (PIN_INPUT | MUX_MODE1) /* (D13) mcasp0_axr1.eQEP0_index */
0x1ac (PIN_INPUT | MUX_MODE1) /* (A14) mcasp0_ahclkx.eQEP0_strobe */
>;
};
eqep0_sleep: eqep0_sleep {
pinctrl-single,pins = <
/* Quadrature Encoder 0 */
0x1a0 (PIN_INPUT | MUX_MODE7) /* (B12) mcasp0_aclkr.eQEP0A_in */
0x1a4 (PIN_INPUT | MUX_MODE7) /* (C13) mcasp0_fsr.eQEP0B_in */
0x1a8 (PIN_INPUT | MUX_MODE7) /* (D13) mcasp0_axr1.eQEP0_index */
0x1ac (PIN_INPUT | MUX_MODE7) /* (A14) mcasp0_ahclkx.eQEP0_strobe */
>;
};
};
am33xx-clocks.dtsi
&scm_clocks {
eqep0_tbclk: eqep0_tbclk@44e10664 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4ls_gclk>;
ti,bit-shift = <0>;
reg = <0x0664>;
};
eqep1_tbclk: eqep1_tbclk@0d8 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4ls_gclk>;
ti,bit-shift = <1>;
reg = <0x0664>;
};
eqep2_tbclk: eqep2_tbclk@0dc {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&l4ls_gclk>;
ti,bit-shift = <2>;
reg = <0x0664>;
};
};
