• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 338 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Booting from NOR Flash Device on the AM3505

Ken Turocy
Prodigy 160 points
Other Parts Discussed in Thread: AM3505

I am considering using a Numonyx Axcell P30-65nm part and connecting it to the GPMC bus in the address/data multiplexed mode for the system's boot device.  Which AM3505 timing diagram should I reference to verify the initial NOR device read cycle?

  • 0
    TI__Genius 9190 points

    Hello Ken,

    I have never worked with this particular device, but from the Numonyx datasheet on page 5 section 1.2, it looks like the part defaults to async page-mode read after power-up and reset, so you will need to use the corresponding timing diagram from the AM35x Data Manual which is Figure 6-9. 

  • 0 in reply to Jeff Culverhouse
    Prodigy 160 points

    Jeff,

    Let say I was using a multiplexed NOR (instead of the non-multiplexed Numonyx part referenced earlier) that defaults to the asynchronous access mode upon reset, would Figure 6-11 in the AM35xx Data Manual be the correct timing diagram to reference for the initial read access after a reset or power on cycle?  If yes, then what are the timing values for the very first read of the NOR device?

    Thanks,

    Ken

     

     

  • 0 in reply to Ken Turocy
    TI__Mastermind 41665 points

    Ken Turocy said:
    would Figure 6-11 in the AM35xx Data Manual be the correct timing diagram to reference for the initial read access after a reset or power on cycle?

    That seems to be the case, as long as your new NOR device can operate in the multiplexed address bus mode shown in the figure.

    Ken Turocy said:
    If yes, then what are the timing values for the very first read of the NOR device?

    The various boot modes that use multiplexed address bus (including the XIP boot mode I would expect for the NOR device) use a EMIF timing configuration described in section 24.4.7.3.1 of the TRM.

    SPRUGR0b said:
    Table 24-32. XIP Timing Parameters
    Parameter     Value [Clock     Register Initialization (i = 0–7)     Reset Value
                            Cycles]
    Write cycle time     17     The GPMC_CONFIG5_i[12:8] WRCYCLETIME bit field is     0x11
                                                set to 0x11.
    Read cycle time     17     The GPMC_CONFIG5_i[4:0] RDCYCLETIME bit field is     0x11
                                                set to 0x11.
    CS low time     1     The GPMC_CONFIG2_i[3:0] CSONTIME bit field is set to     0x1
                                       0x1.
    CS high time     16     The GPMC_CONFIG2_i[12:8] CSRDOFFTIME bit field is     0x10
                                            set to 0x10.
    ADV low time     1     The GPMC_CONFIG3_i[3:0] ADVONTIME bit field is set     0x1
                                           to 0x1.
    ADV high time     2     The GPMC_CONFIG3_i[12:8] ADVRDOFFTIME bit field is         0x2
                                      set to 0x2.
    OE low time     3     The GPMC_CONFIG4_i[3:0] OEONTIME bit field is set to     0x3
                                       0x3.
    OE high time     16     The GPMC_CONFIG4_i[12:8] OEOFFTIME bit field is set     0x10
                                        to 0x10.
    WE low time     3     The GPMC_CONFIG4_i[19:16] WEONTIME bit field is set     0x03
                                        to 0x3.
    WE high time     15     The GPMC_CONFIG4_i[28:24] WEOFFTIME bit field is     0x10
                                            set to 0xF.
    Data latch time     15     The GPMC_CONFIG5_i[20:16] RDACCESSTIME bit field     0x0F
                                                is set to 0xF.