• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 1538 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS/CCSTUDIO: CSL I2C read/write: NACK and timeout handle

Stefano Carlesi
Expert 1325 points

Part Number: CCSTUDIO

Tool/software: Code Composer Studio

I'm using CSL I2C write and read functions, according to the "CSL_I2C_PollExample".

C5517 device,Ic55_csl_3.04 with CCS5.

I noticed that the CSL function does handle START and STOP but looking at the code in csl_i2c.c file it seems to me that it asserts the start and stop bit on the ICMDR register. Reading the C5517 reference manual I understand that the stop bit is sent once the data I2C data couter is 0 (all data is transmitted).

My question is: what happen if a timeout or a NACK occur (no response from slave device)? How should I handle a timeout/NACK condition? I tested this and I saw with the oscilloscope that once a NACK or timeout occur the SCL in held low and the Busy Bit = 1 (that is because the STOP condition has not been sent!). 

I need to use a I2C polling mode.

Thank you,

Stefano

  • 0
    TI__Guru**** 161600 points
    Hi Stefano,

    This is a recommendation from the I2C bus specification:
    "If the SCL or SDA lines are stuck low, the Bus Clear operation is supported. If the clock line (SCL) is stuck low, the preferred procedure is to reset the bus using the hardware reset signal if your I2C devices have hardware reset inputs. If the I2C devices do not have hardware reset inputs, cycle power to the devices to activate the mandatory internal power-on reset (POR) circuit. If the data line (SDA) is stuck low, the master should send nine clock pulses. The device that held the bus low should release it sometime within those nine clocks. If not, use the hardware reset or cycle power to clear the bus."

    Can you try this procedure?

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Expert 1325 points
    Thank you Yordan.
    I already used this solution and to me it is the only one way to get out of the SCL low state. I was expecting CSL functions to somehow handle it, but it seems like user have to reset the I2C manually in case of timeout/NACK.
    This is how I handled the NACK and timeout error:

    Status = I2C_write(I2cWriteBuffer, Length,SlaveAddress, TRUE, startStop, CSL_I2C_MAX_TIMEOUT);
    if(Status == I2C_NACK_ERR)
    {
    ICMDR |= STP;
    ICSTR |= NACK;
    while(ICMDR&MST);
    Error= -1;
    }
    if(Status != CSL_SOK)
    {
    ICMDR &= ~IRS;
    while(ICSTR&BB);
    ICMDR |= IRS;
    Error= -1;
    }

    Do you think this is the right way to handle it?

    Thank you

    Best regards,
    Stefano
  • 0 in reply to Stefano Carlesi
    TI__Guru**** 161600 points
    As I remember from the I2C bus specification, the rule was to wait for 9 clock cycles and see if the interface will overcome the issue and then reset the i2c bus.

    Best Regards,
    Yordan