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No BOOTME on DM648 Lyrtech EVM

Other Parts Discussed in Thread: CDCE906

Hi

I have set the SW2 1-4 = 0011 and have tried

1) the fastboot SW3-3 equal to 0 and get nothing on hyperterm,

2) SW3-3 = 1 and get 'via output on hyperterm.

I have verified that the serial port to hyperterm link works by running the DVDSK uart example.

My switch settings are:

SW2 00111 01000    (should be no hardware flow control)

also tried

SW2 11001 01000    (should be no hardware flow control)

          123..... .......10

SW3 11X10 10000

I have hyperterm set to 115600 baud.

Any ideas? Thanks in advance.

Note that the "Using the DM648 bootloader" doc spraa1jd.pdf says that the bootmode is 1000 for uart. But the rest of the ducment says 0011. I tried 1000 and it didn't work either.

1.10.1 UART Boot Timing
1.11 Ethernet Boot Modes - SGMII0 Only, SGMII0, and SGMII1 (Bootmode[3:0] = 1000b,
Boot-Mode Description www.ti.com
Operationally, UART boot via BOOTMODES[3:0] == 1000b and 1110b are essentially the same. The difference is management of data flow.

 

  • Eddie said:
    I have hyperterm set to 115600 baud.

    Typically we make sure to configure our serial port with the following:

    Bits per Second: 115200
    Data Bits: 8
    Parity: None
    Stop Bits: 1
    Flow Control: None
    Transmit delay: 0 msec/char, 100 msec/line

    I suggest you make sure your configuration looks like this and see if the issue persists.
  • Sorry. Typo, I should have type 115200.

    The configuration is as you stated above. The issue still persists.[:(]

    Thanks

    Eddie

  • Hi Eddie,

    I looked into this a bit this morning, and although I do have an update I do not yet have a resolution. I configured my DIP switches to SW2 = 1100101000 and SW3 = 1111010000 and I do receive output to my terminal; however, this output is always garbage. It does output every few seconds and the garbage remains almost always identical so I am confident this is the BOOTME message. Because the data is garbled, this led me to believe there was a timing issue.

    As you already know the ROM requires a 27MHz input clock which the DM648EVM has. I took a peak at the UART registers after configuring it for UART boot  and I see the DLL register set to 0x31. By my calculations this is what I expect in order for the UART to hit the 115200 mark (((27MHz * 20)/6)/(16*50) = ~115200) but for some reason this is not functioning correctly. I am still debugging to see if I can figure out why this fails.

  • FYI, it looks like the DM648EVM is actually inputting a 33MHz clock to the core instead of a 27MHz clock. The board contains a 27MHz crystal which feeds CDCE906 PLL. I don't know enough about this part to decipher what is happening, but apparently it creates 27MHz clocks for the audio/video parts and a 33MHz clock to the core. This is how the board is able to reach 891MHz (33MHz * 27), but as a result this completely eliminates UART boot mode. Surprisingly the only place I found any reference to this 33MHz clock input was the GEL file (as opposed to the schematic or TRM).

    I don't know if there's a way to change the output of the CDCE906 part and if there is how (I'm assuming it's controlled by the MSP430), but it looks like UART boot is not possible with this board.

  • Hi Tim

    I'm glad you found the issue[:D], but bummed I can't use the board for what we bought it for [:(].

    Are there any HW modifications we can do to get it to run the UART boot mode?

    Also, is your calculation correct?

       (((27MHz * 20)/6)/(16*50) = ~115200)

    I get 112500 baud not the required 115200 baud (I noted you said approximately ( "~") but 112500 seems way off.)

    Cheers

     

  • Agreed that the value is not precisely 115200, but I believe UART can function with up to a 5% tolerance (a 112500 baud rate is about 2.3%).

    I'm checking to see if there's something that can be done to remedy this. The MSP430 controls the CDCE906 before the DSP is released from RESET so if the MSP430 code can be modified then this should be a pretty easy change. I have to see if the MSP430 source code is available (or if Lyrtech ever created an alternate firmware version).

  • Thanks a bunch.[:Y]

  • Hi

    According to the "Using the DM648 Bootloader spraaj1d.pdf doc,

    "The bootloader software does not use auto-baud detect. The UART clock divide registers are set for a
    total divide down value of 15. With a 27-MHz input clock, this yields an approximate baud rate of 115 kbps
    (kilobits per second). The input clock supplied to the UART bypasses the PLL; therefore, this baud rate is
    unaffected by PLL configuration and advantage can be taken of the FASTBOOT modes for faster CPU
    clock."

    With my calculation, 27e6/15 = no where close to 115 kbps[:S]. Your 20/(6*16*50) factor is a lot closer.

    Anyhow, when the document refers to the PLL, is it referring to the PLL driven by CLKIN1 or CLKIN2 pins?

    And thats the same CLKIN you are referring to in the previous emails?

    Thanks.

  • Hi

    I noticed the DM648 data sheet (sprs372d.pdf) Table 3-3 says FASTBOOT=0 hence it is not available for the UART. Yet the "Using the DM648 Bootloader spraaj1d.pdf says that FASTBOOT can be 0 or 1.

    Which is correct?

    What happens if FASTBOOT = 0? The "using the DM648 bootloader ..." doc only states what happens when FASTBOOT=1.

    Thanks

     

     

  • Hi

    (Yet another question)

    I was wondering where your (((27MHz * 20)/6)/(16*50) = ~115200) numbers came from.

    where

    - 20: Due to FASTBOOT which sets SYSCLK multiplier to 19 (using thebootloader doc spraaj1d.pdf)

    - 6: Due to UART bit clock = 1/6th of SYSCLk (From the UART GUIDE spruel8a.pdf)

    - 16: ??

    - 50: You mentioned the clk divide register was set to 0x31 (49). I can't find any documentation on this.

    In the "Using the Bootloader..." doc Sec 1.10.1, it states that the UART clock divide registers are set to 15. Could you help me understand how the clock dividing works?.[:S]

    If FASTBOOT=0, then the 6 factor is removed from the equation and the divider is not set to 0x31?

    Many thanks

     

  • Eddie said:
    With my calculation, 27e6/15 = no where close to 115 kbpsTongue Tied. Your 20/(6*16*50) factor is a lot closer.

    Anyhow, when the document refers to the PLL, is it referring to the PLL driven by CLKIN1 or CLKIN2 pins?

    And thats the same CLKIN you are referring to in the previous emails?



    Eddie said:
    What happens if FASTBOOT = 0? The "using the DM648 bootloader ..." doc only states what happens when FASTBOOT=1.


    Eddie said:
    I was wondering where your (((27MHz * 20)/6)/(16*50) = ~115200) numbers came from.


    My calculations came from peeking at the source for the ROM bootloader (which I am unable to provide). The datasheet is apparently incorrect regarding FASTBOOT with the UART boot as the boot code indeed does allow FASTBOOT to be '1.' When FASTBOOT = 1 the PLLM register is set to 0x13 which translates to a times 20 on the PLL. This is why the 27MHz clock is multiplied in my equation by 20. Note that this is discussed in section 1.10 of the bootloader app note.

    Because the UART module runs off SYSCLK3 the output of the PLL is then divided by 6. The value of 16 comes from the OSM_SEL field of the MDR register (set to '0' by default and not modified by the bootloader). Finally, the 50 value comes from how the bootloader configures the DLL UART register - 0x31 if OSM_SEL = 1, 0x3C if OSM_SEL = 0. The UART clock numbers derived from this calculation will equal roughly 115200. I'm not sure why section 1.10.1 suggest a total divide down value of 15 but this is wrong.

    Finally, note that when FASTBOOT = 0 the UART will be driven off a 27M / 6 clock, thus a much smaller divider can be used (27M / 6 / 13 / 3= ~115200).

  • Thanks TIm

    Your comments really help to bring clarity to the documentation errors![:D]

    Cheers
    Eddie

  • Hi Tim

    Any luck finding a fix?[*-)] Our new hardware is coming out fab in a couple weeks and I'd sure like to have verified that I can load my test apps using the EVM UART boot mode.

    Cheers

    Eddie

  • Eddie,

    I haven't heard back from Lyrtech yet. I'll be sure to let you know when I do hear anything back. You may want to submit this question to them yourself (who knows, it may speed up the process [:)] ).

  • Yiks.[:S] The last time I sent them a request it took 2 weeks for a response. I'd better send it pronto.

    Cheers

  •  

    RS232 boot mode is not supported on DM648 evm (all rev including C2).

    1- As a workaround, if user want to customize an evm board to run application at startup, he could program his application easily in onboard evm flash memory (32 MB) and configure the dip switches to boot direct from flash. Provided Lyrtech "evmupdater" application can be easily used to program any user ".out" application in flash memory.

    2- If a user really want to send code through rs232, he could program a small application in flash memory that configures rs232 correctly then wait from the serial port to download some binary file sent by user application. But this should all be done by user dsp application without using the dsp boot rom.

    For additionnal support, please contact support@lyrtech.com

     

  • Thanks for suggesting a.......... solution..............I think[:S]

  • The response I received from Lyrtech:

    Dear Edward,

    Uart boot mode is unsupported on the EVM. EVM clocks (DSP/VIDEO/AUDIO) are
    all based on a 33 MHz clock by design because 27 MHz clock does not allow to
    run the cpu at maximum speed. 27 MHz clock is unsupported on the EVM.

    As a suggested workaround:

    1- you can boot your application from flash memory instead (using lyrtech
    evmupdater tool allows to burn an application in flash memory easily from
    your application .out file, using a jtag emulator).

    2- Another but more difficult work around would be to write a small
    application that would initialize the evm serial port say at 115200 Bauds,
    than wait for a binary transfer received from the serial port. These small
    apps could simply dump the binary received at fixed location in DDR2 or L2
    memory (depending of your requirement). You can look at DVSDK
    "C:\dvsdk_1_11_00_00_DM648\pspdrivers_1_10_00\packages\ti\sdo\pspdrivers\sys
    tem\dm648\bios\evmDM648\uart"

    UART example application for UART communication (path is for latest 1.11
    DVSDK). In this case, you would download your binary application and then
    jumping to execute it after. These workarounds do not rely on the rom
    bootloader uart mode.

    3- Ethernet rom boot mode can also be used but would require writes a more
    complicated PC computer application.

    Hope this information help

  • Hi

    Since I have to write my own flashed UART bootloader, is there example code that does what the DM648 resident UART bootloader does? What I'm looking for is something that parses the AIS format so that the UART reading software knows how many bytes it is expecting to receive?

    Thanks

  • Eddie,

    There is an AIS parser in the DM648 DVSDK installer (C:\dvsdk_1_11_00_00_DM648\flashutil\DM647_8\CCS\UBL\src). You can use this to parse the AIS codes in your secondary UART boot code.