This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DDR2 problem on 320C6424

The test program is loaded correctly and works from DDR2 memory. But is it worth to include DMA (EDMA3) exchange with DDR2 immediately dies. He dies when transferring buffer from L2 to DDR2.
What to do - I'll never know. Quartz 25MHz. PLL is programmed to 162.5 Mhz
Initialization is as follows:


g_setup_ddr2( 162.5 )

g_setup_ddr2( float freq )
{
#define DDR_SDBCR *( unsigned int* )( 0x20000008 )
#define DDR_SDRCR *( unsigned int* )( 0x2000000c )
#define DDR_SDTIMR *( unsigned int* )( 0x20000010 )
#define DDR_SDTIMR2 *( unsigned int* )( 0x20000014 )
#define DDR_DDRPHYCR *( unsigned int* )( 0x200000e4 )
#define DDR2_PBBPR *( unsigned int* )( 0x20000020 )

#define DDR_VTPIOCR *( unsigned int* )( 0x200000f0 )
#define DDR_DDRVTPR *( unsigned int* )( 0x01c42038 )
#define DDR_DDRVTPER *( unsigned int* )( 0x01c4004c )

int dummy_read;
int pch_nch;

GEL_TextOut( "Setup DDR2 (%f MHz + 32-bit bus)... ",,,,, freq );

/*
* Step 1 - Setup PLL2
* Step 2 - Enable DDR2 PHY
*/
g_psc_change_state( 13, 3 );

/*
* Step 3 - DDR2 Initialization
*/
DDR_DDRPHYCR = 0x50006405; // DLL powered, ReadLatency=5
DDR_SDBCR = 0x00138821; // DDR Bank: 32-bit bus, CAS=4, *0x00138822
// 4 banks, 1024-word pg
DDR2_PBBPR = 0x20;
DDR_SDTIMR = 0x16493200; // DDR Timing
DDR_SDTIMR2 = 0x000CC702; // DDR Timing
DDR_SDBCR = 0x00130821; // DDR Bank: cannot modify *0x00130822
DDR_SDRCR = freq * 7.8 + 1; // Refresh Control [ 7.8 usec * freq ] *7.8

/*
* Step 4 - Dummy Read from DDR2
*/
dummy_read = *( int* )0x80000000;

/*
* Step 5 - Soft Reset ( SYNCRESET followed by ENABLE ) of DDR2 PHY
*/
g_psc_change_state( 13, 1 );
g_psc_change_state( 13, 3 );

/*
* Step 6 - Enable VTP calibration
* Step 7 - Wait for VTP calibration ( 33 VTP cycles )
*/
DDR_VTPIOCR = 0x201f;
DDR_VTPIOCR = 0xa01f;
g__wait( 1500 );

/*
* Step 8 - Enable access to DDR VTP reg
* Step 9 - Reat P & N channels
* Step 10 - Set VTP fields PCH & NCH
*/
DDR_DDRVTPER = 1;
pch_nch = DDR_DDRVTPR & 0x3ff;
DDR_VTPIOCR = 0xa000 | pch_nch;

/*
* Step 11 - Disable VTP calibaration
* - Disable access to DDR VTP register
*/
DDR_VTPIOCR &= ~0x2000;
DDR_DDRVTPER = 0;

GEL_TextOut( "[Done]\n" );
}

Chip memory 2 x MT47H16M16-4 MEG X 16 X 4 (32-bit mode)

Do I need to program the internal registers in the memory (DDR2) chip (load mode), if so, how?

  • Vitaliy said:
    The test program is loaded correctly and works from DDR2 memory.

    Is this your own board or an EVM? If this is your own board, I recommend writing or finding online a memory test program that writes and reads the entire memory and also that does very fast accesses to make sure the DDR2 is working well. If the DDR2 is working well, then the initialization may not be the problem. EDMA3 may operate the bus at a higher bandwidth, so it is still possible but less likely.

    Vitaliy said:
    But is it worth to include DMA (EDMA3) exchange with DDR2 immediately dies. He dies when transferring buffer from L2 to DDR2.

    I think this means that when you try to do an EDMA3 transfer from L2 to DDR2 then "he" "dies". But I do not know what "he" means other than the DSP in general or what "dies" means other than it does not work the way you want it to work. Please explain more about the problem.