CCS/AM5726: DSP memory access

Allen35065

Expert 4305 points

Part Number: AM5726

Tool/software: Code Composer Studio

Hi expert,

I'm debugging DSP code on AM5726 IDK board and had a problem on memory access. As below is my test steps.

1. I used gel file on ARM to initialize DSP core, and wrote 0x50505050 on 0x00800000 of DSP1.

2. Then I read 0x40800000 whichi is L3 address of DSP1 L2 RAM from DSP1, but there is no correct value.

3. Read 0x40800000 from DSP2, the value is correct.

Is there any restriction to access address 0x40800000 from DSP1 core?

Regards,

Allen

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

The AM57x team have been notified. They will respond here.

0 jian35385 over 8 years ago in reply to Biser Gatchev-XID

TI__Mastermind 23125 points

Allen,

Good to hear from you since a long time. Sorry for the delayed response.

The DSP1->L3->DSP1_L2 is a forbidden path from the connectivity matrix. You can find the full matrix in the TRM, Table 14-3, where each DSP's MDMA port is not connected to its own slave SDMA port. So a user should only access its own L2 memory using internal CorePac memory map, instead of via L3 then back.

Please let me know if this is clear, or if you can not find the matrix table.

regards

Jian

0 Allen35065 over 8 years ago in reply to jian35385

TI__Expert 4305 points

Hi Jian,

It's a pleasure to hear from you. This is quite clear. Thank you.

Regards,

Allen

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CCS/AM5726: DSP memory access