AM5728: PCIe access error

The software team have been notified. They will respond here.

Hi, Sung-IL,

The error is from l3_interrupt_handler() and seems to be caused by DSP1 acessing L4_CFG through MDMA interface. I suspect it is the memory used by DSP still under ARM MMU protection. You may want to configure those area used by PCIe in DSP resource table. I'll have DSP engineer to take a closer look at this one.

Rex

Hi,

Can you confirm: if in the Linux kernel/dts you disabled the PCIE? And you used the P-SDK RTOS PCIE example code to do PCIE initialization on DSP side? Do you use IPC to download DSP code from Linux side?

Regards, Eric

Hi,

Thanks for the info! Then, they need IPC resource table: processors.wiki.ti.com/.../IPC_Resource_customTable to build into the DSP side code. Do they have that?

Regards, Eric

Hi Eric,

Yes. they have IPC resource table, and attached it as below.

could you please check their IPC resource table?

0020.rsc_table_vayu_dsp.h

Thanks and Best Regards,

SI.

Hi,

Have you checked this IPC resource table?
Is there any other thing should be checked to solve this issue?

Thanks and Best Regards,
SI.

Hi,

The error came from accessing L3 main 0x4400_0000. The resource table they created doesn't have such L3_MAIN entry. Can they double check and add?

Regards, Eric

Hi Eric,

I'm pushing customer to add L3_MAIN entry and test again, but they want to check/understand if this is right approach.
And also, they have not seen this issue before their modification removing all related things from ARM and curious why this issue was not occurred at that time.
Could you please let me know your idea on this?


Thanks and Best Regards,
SI.

Hi,

When the PCIE is removed from Linux device tree, the PCIE clock, configuration and data space access is protected by MMU.

Now the PCIE initialization is done by DSP side, the DSP code would setup PLL clock, PCIE configuration registers and data memory. In the resource table, I saw PCIE configuration and data space are clearly mapped. Please check pcie_sample_board.c under TI RTOS PCIE driver, to make sure the address used by PLL setup is also mapped in resource table (SOC_L3INIT_CM_CORE_BASE, SOC_OCP2SCP3_BASE, etc ). Perhaps, you can first download a dummy DSP image to make sure there is no such 4400000.ocp access violation first. Then, add the PCIE PLL code, to see if the access violation occurred. If yes, add the entry to fix it.

The PCIE doesn't access 44000000 address, I was wrong early to add an entry for 44000000, sorry for this!

Regards, Eric