Linux/DRA712: mcasp device tree clock properties

Hi Christian,

I have forwarded your question to McASP expert.

Regards,
Yordan

Thanks for your answer.

Diiging deeper, for DRA72-EVM (dra72-evm-common.dtsi), we understand from

&mcasp3 {
    #sound-dai-cells = <0>;
    assigned-clocks = <&mcasp3_ahclkx_mux>;
    assigned-clock-parents = <&atl_clkin2_ck>;

...
};

mcasp3 use ahclkx_mux as reference clock, which one takes atl_clk as source.

From Clock Tree Tool for DRA71x SR2.0 we understand that atl_clk2 is attached to atl_clk2_pin. It match with EVM CPU_Schematic (page 3). This pin is an output, so we understand that it can no be a clk reference for mcasp3. We are missing anything?

On the other hand, atl_clkin2_ck device tree node use atl_gfclk_mux as clock source, so it is not atteched to atl_clk_pin?

    atl_clkin2_ck: atl_clkin2_ck {
        #clock-cells = <0>;
        compatible = "ti,dra7-atl-clock";
        clocks = <&atl_gfclk_mux>; 
    };                                                    

   and atl_gfclk_mux has "clocks" as source, but we can't find any node configuring it                                                        

    atl_gfclk_mux: atl_gfclk_mux {
        #clock-cells = <0>;
        compatible = "ti,mux-clock";
        clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
        ti,bit-shift = <26>;
        reg = <0x0c00>;
    };

Could you help us to understand which clock source is used by mcpas3 and where it is configured?

Christian,

The ATL clock (atl_clkin2_ck) is routed to the McASP AHCLKX (for BCLK/FSYNC generation) as well as to external pin atl_clk2_pin (which is connected to the aic3106 codec MCLK in the EVM board).

The atl_gfclk is being reparented to the dpll_abe_m2_ck clock in the dra72-evm-common.dtsi file:

&atl {
	assigned-clocks = <&abe_dpll_sys_clk_mux>,
			  <&atl_gfclk_mux>,
			  <&dpll_abe_ck>,
			  <&dpll_abe_m2x2_ck>,
			  <&atl_clkin1_ck>,
			  <&atl_clkin2_ck>;
	assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
	assigned-clock-rates = <0>, <0>, <180633600>, <361267200>,
			       <11289600>, <11289600>;

	status = "okay";

	atl2 {
		bws = <DRA7_ATL_WS_MCASP2_FSX>;
		aws = <DRA7_ATL_WS_MCASP3_FSX>;
	};
};

In summary, the configured McASP3 clock tree looks like: (ABE DPLL) -> dpll_abe_m2_ck -> atl_gfclk_mux -> (ATL module) -> atl_clkin2_ck -> mcasp3_ahclkx_mux -> (McASP AHCLKX)

Thanks for your reply Misael.

We have to achieve a deep understanding about mcasp clock tree, because in our custom design OSC=19.2M and atl_clk2_pin must no be used for clocking.

By Clock Tree Tool (CTT) for DRA71x SR2.0 and TRF, we understand that DPLL_ABE provides DPLL_ABE_CLKOUT_M2=PER_ABE_X1_GFCLK and DPLL_ABE_CLKOUTX2_M2=PER_ABE_X2_CLK.
We didn't find EVM DT configuration for DPLL_ABE so we assume default values (SYS_CLK_Source 20MHz for both of them).
From CTT DPLL_ABE_CLKOUT_M2=PER_ABE_X1_GFCLK=PER_ABE_X1_DCLK this signal end at MUX_CLKOUTMUXx_CLK. We can not find atl_ endpoint

From TRF Figure 3-35 we understand that PER_ABE_X1_GFCLK reach to ATL_GFCLK mux, but we didn't find how it reaches to MCASP.

Could you provide any information to relate TRF (ATL chapter has only one page) with DT.


Thanks in advance

Thanks a lot for your help

We are trying to set MCASP3 CLKX and CLKR generated internally (first scenario depicted ch 24.6.4.2). From this paragraph and with Fig 24-114 we understand that clocks (rx tx) are derived from AUXCLK=MCASPi_FCLK.
From Fig 3-42 we understand that MCASP3_AUX_GFCLK can be derived from PER_ABE_X1_GFCLK, VIDEO1_CLK(/divider), HDMI_CLK(/divider)

In our design VIDEO_CLK and HDMI_CLK can no be used, so using PER_ABE_X1_GFCLKwith the same configuration as EVM (20MHz from OSC)

We configure DT as

&mcasp3 {
	#sound-dai-cells = <0>;
	assigned-clocks = <&mcasp3_aux_gfclk_mux>;
	assigned-clock-parents = <&per_abe_x1_gfclk2_div>;

	status = "okay";

	op-mode = <0>;
	tdm-slots = <2>;
	serial-dir = <1 2 0 0>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

	sound_blue:sound@0 {
		compatible = "simple-audio-card";
		simple-audio-card,name = "bluetooth-audio-board";
		simple-audio-card,widgets =
        "Headphone",   "Playback",
        "Microphone",  "Capture";
		simple-audio-card,routing =
        "Playback",    "TX",
        "Capture",     "RX";  
     simple-audio-card,format = "i2s";
     simple-audio-card,bitclock-master = <&sound_blue_master>;
     simple-audio-card,frame-master = <&sound_blue_master>;
		simple-audio-card,bitclock-inversion;

		sound_blue_master: simple-audio-card,cpu {
			sound-dai = <&mcasp3>;
			system-clock-frequency = <20000000>;
		};

     sound_blue_slave: simple-audio-card,codec {
        sound-dai = <&codec_blue>;
		};
	};

   codec_blue: bt-sco-pcm {
      #sound-dai-cells = <0>;
      compatible = "linux,bt-sco";
   };

When we try to play pcm16b16kstereo file, we get

"davinci-mcasp 48468000.mcasp: Too fast reference clock ..."

Diiging deeper, this is due Table 24-510. MCASP_AHCLKXCTL bit 15 is not set. It is set by davinci_mcasp_set_sysclk(..., ..., ..., dir), but

¿how can we set this field by device tree?