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PROCESSOR-SDK-AM335X: DDR DPLL settings

Chris Karaplis
Expert 1400 points

Part Number: PROCESSOR-SDK-AM335X

I am updating from U-Boot 2015.07 to 2017.01 and there have been many changes to the way the clocks were setup. The CLK_M_OSC on my board is 25MHz and set as such in the U-boot configuration. However, when the DDR DPLLs are set up in the SPL, the processor hangs at with an invalid instruction exception. Looking into the clock settings in clock_am33xx.c, there are the dpll_params for 303MHz, 400Hz and 266Mhz. My board is going to run at 400MHz, so this is the table as defined:

const struct dpll_params dpll_ddr3_400MHz[NUM_CRYSTAL_FREQ] = {
{125, 5, 1, -1, -1, -1, -1}, /*19.2*/
{50, 2, 1, -1, -1, -1, -1}, /* 24 MHz */
{16, 0, 1, -1, 4, -1, -1}, /* 25 MHz */
{200, 12, 1, -1, 4, -1, -1} /* 26 MHz */
};

So seemingly for a 25MHz CLK_M_OSC it would take the third element, which makes sense:

m = 16, n = 0 => m * 25 / n + 1 = 16 * 25 / 1 = 400MHz. Great right?

But why is M4 set. Correct me if I am wrong, but I don't see M4 connected to anything in the TRM. And if I go back to 2015.07 U-Boot the DLL params are described as:

const struct dpll_params dpll_ddr_bone_black = {400, OSC-1, 1, -1, -1, -1, -1};

Which seems to make more sense. Nonetheless if I change M4 from 4 to -1 in the new U-Boot everything works and the board comes up fine. Is this a typo in the configuration?

Thanks,

Chris

  • 0
    TI__Guru**** 393215 points
    The software team have been notified. They will respond here.
  • 0
    TI__Guru**** 170625 points

    Hi Chris,

    Yes, your change (from 4 to -1) seems to be correct. DPLL_DDR do not support M4 divider. Only DPLL_CORE support M4 post-divider, and its value is configured in register CM_DIV_M4_DPLL_CORE.

    The u-boot code is trying to configure M4 divider for DPLL_DDR also, in the below function, and the error come up.

    static void setup_post_dividers(const struct dpll_regs *dpll_regs, const struct dpll_params *params)

    {

    /* Setup post-dividers */

    if (params->m2 >= 0)

    writel(params->m2, dpll_regs->cm_div_m2_dpll);

    if (params->m3 >= 0)

    writel(params->m3, dpll_regs->cm_div_m3_dpll);

    if (params->m4 >= 0)

    writel(params->m4, dpll_regs->cm_div_m4_dpll);

    if (params->m5 >= 0)

    writel(params->m5, dpll_regs->cm_div_m5_dpll);

    if (params->m6 >= 0)

    writel(params->m6, dpll_regs->cm_div_m6_dpll);

    }

     

    I will notify the PSDK team for this issue, and this should be fixed in some of the next versions.

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Expert 1400 points

    Thanks for the confirmation Pavel.

    Regards,

    Chris