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Running code from IRAM in the C64x+ core within the OMAP3530

Len Koss
Intellectual 300 points
Other Parts Discussed in Thread: OMAP3530

Hi,

I'm currently using a Mistral Board with OMAP3530 and CCS ver 4.1.2 and BIOS 5.41.04.18.  Also, my application is small enough that it can fit and run out of IRAM.  The problem I'm having is that if I start with Cache disabled in my project and after a cold start execute directly from IRAM, the code runs 4x slower than if I run from a cold start with Cache initially enabled in my project.  What's puzzling is that the code still continues to run at the faster rate even when the project is subsequently halted, rebuilt and run with Cache disabled.  BTW, the board was never reset or powered down after the initial power-up.  So the questions I have are the following:

1)  With Cache initially disabled, why does the code run slow from IRAM immediately after power-up or from a hard reset?

2)  Why does the code speed up after enabling Cache then rebuilding and re-running the code.

3)  Why does the code continue to run fast after subsequently disabling Cache then rebuilding and once again re-running the same code from IRAM?  

 

As long as I'm running from IRAM, i would expect the same performance immediately after a cold start whether or not Cache is initially enabled.

 

Thanks,

Len  

 

  • 0
    TI__Mastermind 18320 points

    Is this question still open?  I'm wondering if it should be moved to the OMAP35xx forum instead of the BIOS forum to get a faster response...

     

  • 0 in reply to David Friedland
    Intellectual 300 points

     

    David,

    The question is still open because I haven't seen the response.  Where's the link to the response.

     

    Thanks,

    Len

  • 0 in reply to Len Koss
    TI__Mastermind 20805 points

    Len --


    How are you enabling and disabling the cache?  Are you doing this thru CCS user interface?  Or using the BIOS config tool?  Or BCACHE runtime API?

    The OMAP3430 had 2 levels of cache.  I suspect that the L1D and/or L1P cache state is changing somehow in the sequence you are describing.  You should be able to see these memory mapped registers in a memory window within CCS.  There might be a register view that shows them.  I don't remember and I don't have the right setup here right now to check.

    IRAM is on-chip L2 SRAM that can be configured as cache or RAM.   If you have it as RAM, then the L1D/P can still affect your performance.

    You can specify cache size for L1P/D in the below dialog box in your config.

    Regards,
    -Karl-

  • 0 in reply to Karl Wechsler
    Intellectual 300 points

    Karl,

    Thanks for the response.  Actually, I set up the Cache using the gconf interface and I'm using the same configuration as the display above.  But i still can't understand why the algorithm would run slower when I move the time critical portion of the code from DDR to L2 SRAM.  I was under the impression that a shorter hop to the L1P cache would result in an increase in speed.  Could you shed some light on why I'm observing a degradation in performance when the executable code is inside?  I'm trying to squeeze every once of speed out of this algorithm so I'd like to try and get a better handle on this.  BTW, I can easily view the memory mapped registers using CCS so which ones do I need to view and what should I be looking for?

     

    Thanks,

    Len