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TCI6630K2L: ARM PLL Initialization Sequence

Thibaut B
Prodigy 80 points
Part Number: TCI6630K2L

Hi,

I saw that the SPRUGV2I document (KeyStone Architecture Phase-Locked Loop (PLL)) has been recently updated with a new step inside the ARM PLL Initialization Sequence:

"Added Set CHIPMISCCTL1[13]=0 (enable glitchfree bypass) to new step 2".

On the TCI6630K2L, there is no bit 13 in the CHIP_MISC_CTL1 register.

This has been already disscussed here: https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/260831?tisearch=e2e-sitesearch&keymatch=CHIPMISCCTL1

But no answer has been posted.

How can we enable the glitchfree bypass on the Lamarr?

Regards,
Thibaut