RTOS/DRA756: HOW can I load dspdce fireware on DSP2 of J6

user5163780

Part Number: DRA756

Tool/software: TI-RTOS

When we use J6 DSP, we cannot load dspdce firmware on DSP2 correctly. Thank you!

We compile the most primitive dspdce_1_00_00_08 on ti-processor-sdk-linux-automotive-dra7xx-evm-03_01_00_03, and generate the dra7xx-c66x-dsp.xe66.
Using the following command to load the firmware to DSP1, we can find the device node rpmsg-dce-dsp, and also run normally.

Echo 40800000.dsp > unbind
Ln -s /opt/demos/sv/dra7xx-c66x-dsp.xe66 /lib/firmware/dra7-dsp1-fw.xe66
Echo 40800000.dsp > bind

But, when we change the config.bld and the dce_dsp.cfg file (see Annex) related settings, recompile dspdce_1_00_00_08 to generate dra7xx-c66x-dsp.xe66, and then,
using the following command to load the firmware to DSP2, it can not generation device node rpmsg-dce-dsp, and can not run normally.

Echo 41000000.dsp > unbind;
Ln -s /opt/demos/sv/dra7xx-c66x-dsp.xe66 /lib/firmware/dra7-dsp2-fw.xe66
Echo 41000000.dsp > bind

We also encounter the same problem in ti-processor-sdk-linux-automotive-dra7xx-evm-03_02_00_03.

config.bld

==========================================================================

var Build = xdc.useModule('xdc.bld.BuildEnvironment');
var commonBld = xdc.loadCapsule("../build/common.bld");
var commonOpts = "-g";
var hw_VAYU = 2;
var ES10 = 1;

for (x = 0; x < arguments.length; x++)
{
if (arguments[x].match(/^trace_level=/) )
{
// [1] operation is used on the return value of split(), which is an
// array.
var trace_level = arguments[x].split("=")[1];
}
}

/************************************
* Memory Map Information
************************************/
/* Memory Map for ti.platforms.evmDRA7XX:dsp1
*
* --- External Memory ---
* Virtual Physical Size Comment
* ------------------------------------------------------------------------
* 9500_0000 ????_???? 20_0000 ( ~2 MB) EXT_CODE
* 9520_0000 ????_???? 20_0000 ( 2 MB) EXT_DATA
* 9540_0000 ????_???? 280_0000 ( 40 MB) EXT_HEAP
* 9F00_0000 9F00_0000 6_0000 ( 384 kB) TRACE_BUF
* 9F06_0000 9F06_0000 1_0000 ( 64 kB) EXC_DATA
* 9F07_0000 9F07_0000 2_0000 ( 128 kB) PM_DATA (Power mgmt)
*/
var evmDRA7XX_ExtMemMapDsp1 = {
EXT_CODE: { name: "EXT_CODE", base: 0x95000000, len: 0x200000, space: "code", access: "RWX" },
EXT_DATA: { name: "EXT_DATA", base: 0x95200000, len: 0x00200000, space: "data", access: "RW" },
EXT_HEAP: { name: "EXT_HEAP", base: 0x95400000, len: 0x02800000, space: "data", access: "RW" },
TRACE_BUF: { name: "TRACE_BUF", base: 0x9F000000, len: 0x00060000, space: "data", access: "RW" },
EXC_DATA: { name: "EXC_DATA", base: 0x9F060000, len: 0x00010000, space: "data", access: "RW" },
PM_DATA: { name: "PM_DATA", base: 0x9F070000, len: 0x00020000, space: "data", access: "RWX" }
};

Build.platformTable["ti.platforms.evmDRA7XX:dsp1"] = {
externalMemoryMap: [
[ "EXT_CODE", evmDRA7XX_ExtMemMapDsp1.EXT_CODE ],
[ "EXT_DATA", evmDRA7XX_ExtMemMapDsp1.EXT_DATA ],
[ "EXT_HEAP", evmDRA7XX_ExtMemMapDsp1.EXT_HEAP ],
[ "TRACE_BUF", evmDRA7XX_ExtMemMapDsp1.TRACE_BUF ],
[ "EXC_DATA", evmDRA7XX_ExtMemMapDsp1.EXC_DATA ],
[ "PM_DATA", evmDRA7XX_ExtMemMapDsp1.PM_DATA ]
],
codeMemory: "EXT_CODE",
dataMemory: "EXT_DATA",
stackMemory: "EXT_DATA",

// modified by baron 20170425
l1PMode: "32k",
l1DMode: "32k",
l2Mode: "256k"
};

Build.platformTable["ti.platforms.evmDRA7XX:dsp2"] = Build.platformTable["ti.platforms.evmDRA7XX:dsp1"];

var TargetBuild = commonBld.getTargetBuild(arguments);
commonOpts += " -DHOST_TYPE=HOST_UNKNOWN "

/************************************
* Setup for dsp target
************************************/
var dsp_tgt = xdc.useModule('ti.targets.elf.C66');
dsp_tgt.rootDir = java.lang.System.getenv("C66XCGTOOLSPATH");
dsp_tgt.ccOpts.suffix += " --gcc -D___DSPBIOS___ -DDSP";
dsp_tgt.ccOpts.suffix += " -ms ";
//dsp_tgt.ccOpts.suffix += " -pden -pds=48 ";
//dsp_tgt.ccOpts.suffix += " -pdew "; //Convert warn to err; Supported in 4.9 version
dsp_tgt.ccOpts.suffix += commonOpts;
dsp_tgt.lnkOpts.suffix += " -x ";
dsp_tgt.lnkOpts.prefix += " --retain=.resource_table";
//dsp_tgt.lnkOpts.prefix += " --zero_init=off ";
//dsp_tgt.lnkOpts.prefix += " --cinit_compression=off";

dsp_tgt.platforms = [
"ti.platforms.evmDRA7XX:dsp2", //0
];

/***************** Tracing ********************/
if(trace_level == 0) {
dsp_tgt.ccOpts.suffix += " -DDCE_DEBUG_LEVEL=0";
} else if(trace_level == 1) {
dsp_tgt.ccOpts.suffix += " -DDCE_DEBUG_ENABLE";
dsp_tgt.ccOpts.suffix += " -DDCE_DEBUG_LEVEL=1";
} else if(trace_level == 2) {
dsp_tgt.ccOpts.suffix += " -DDCE_DEBUG_ENABLE";
dsp_tgt.ccOpts.suffix += " -DDCE_DEBUG_LEVEL=2";
} else if(trace_level == 3) {
dsp_tgt.ccOpts.suffix += " -DDCE_DEBUG_ENABLE";
dsp_tgt.ccOpts.suffix += " -DDCE_DEBUG_LEVEL=3";
} else if(trace_level >= 4) {
dsp_tgt.ccOpts.suffix += " -DDCE_DEBUG_ENABLE";
dsp_tgt.ccOpts.suffix += " -DDCE_DEBUG_LEVEL=4";
}
/***************** Tracing ********************/
{
HwType = hw_VAYU;
HwVer = ES10;
var build_vayu = true;
print("Selected Vayu for ES10");

dsp_tgt.ccOpts.suffix += " -DBUILD_FOR_VAYU";
dsp_tgt.ccOpts.suffix += " -DVAYU_ES10";
dsp_tgt.platform = dsp_tgt.platforms[0];
}

Build.targets = [
dsp_tgt,
];

var Pkg = xdc.module("xdc.bld.PackageContents");

==========================================================================

dce_dsp.cfg

===========================================================================

/* -------------------------------- DSP ----------------------------------*/
MultiProc.setConfig("DSP2", ["HOST", "IPU2", "IPU1", "DSP2", "DSP1"]);

===========================================================================

over 7 years ago

0 Ramprasad over 7 years ago

TI__Mastermind 30480 points

Hi,
Just with these changes it will not be possible for you to load dspdce firmware on dsp2.
dspdce fixes the address carve-out to 0x99000000 in platform/ti/dce/baseimage/custom_rsc_table_vayu_dsp.h and remote proc driver also
informed to use this address for DSP1.

Refer /arch/arm/boot/dts/dra7-evm.dts reserved_mem section.

Thanks

0 user5163780 over 7 years ago in reply to Ramprasad

Prodigy 40 points

HI，can you say more clearly? I change the address to 0x99000000, I can not load dspdce fireware on DSP2 of J6 also.

0 user5163780 over 7 years ago in reply to user5163780

Prodigy 40 points

HI, Ramprasad, Thanks for your reply!

In addition to the above changes, I change the address carve-out to 0x9F000000 in platform/ti/dce/baseimage/custom_rsc_table_vayu_dsp.h , but it can not load dspdce fireware on DSP2 of J6 also.

Can you provide a pakeage of dspdce_1_00_00_08 which can load on DSP2 of J6 ?

/*
* ======== custom_rsc_table_vayu_ipu.h ========
*
* Define the VAYU/DRA7xx custom resource table entries for all IPU cores. This will be
* incorporated into corresponding base images, and used by the remoteproc
* on the host-side to allocated/reserve resources.
*
*/

#ifndef __CUSTOM_RSC_TABLE_VAYU_DSP_H__
#define __CUSTOM_RSC_TABLE_VAYU_DSP_H__

#include <ti/ipc/remoteproc/rsc_types.h>

/* DSP Memory Map */
#define L4_DRA7XX_BASE 0x4A000000

/* L4_CFG & L4_WKUP */
#define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE)
#define DSP_PERIPHERAL_L4CFG 0x4A000000

#define L4_PERIPHERAL_L4PER1 0x48000000
#define DSP_PERIPHERAL_L4PER1 0x48000000

#define L4_PERIPHERAL_L4PER2 0x48400000
#define DSP_PERIPHERAL_L4PER2 0x48400000

#define L4_PERIPHERAL_L4PER3 0x48800000
#define DSP_PERIPHERAL_L4PER3 0x48800000

#define L4_PERIPHERAL_L4EMU 0x54000000
#define DSP_PERIPHERAL_L4EMU 0x54000000

#define L3_PERIPHERAL_DMM 0x4E000000
#define DSP_PERIPHERAL_DMM 0x4E000000

#define L3_PERIPHERAL_ISS 0x52000000
#define DSP_PERIPHERAL_ISS 0x52000000

#define L3_TILER_MODE_0_1 0x60000000
#define DSP_TILER_MODE_0_1 0x60000000

#define L3_TILER_MODE_2 0x70000000
#define DSP_TILER_MODE_2 0x70000000

#define L3_TILER_MODE_3 0x78000000
#define DSP_TILER_MODE_3 0x78000000

#define DSP_MEM_TEXT            0x95000000
#define DSP_MEM_IOBUFS          0x80000000
#define DSP_MEM_DATA            0x95200000
#define DSP_MEM_HEAP            0x95400000

#define DSP_MEM_IPC_DATA        0x9F000000
#define DSP_MEM_IPC_VRING       0xA0000000
#define DSP_MEM_RPMSG_VRING0    0xA0000000
#define DSP_MEM_RPMSG_VRING1    0xA0004000
#define DSP_MEM_VRING_BUFS0     0xA0040000
#define DSP_MEM_VRING_BUFS1     0xA0080000

#define DSP_MEM_IPC_VRING_SIZE SZ_1M
#define DSP_MEM_IPC_DATA_SIZE SZ_1M

#define DSP_MEM_TEXT_SIZE (SZ_1M * 2)

#define DSP_MEM_DATA_SIZE       (SZ_1M * 2)
#define DSP_MEM_HEAP_SIZE       (SZ_1M * 40)
#define DSP_MEM_IOBUFS_SIZE     (SZ_1M * 90)

#define VAYU_DSP_1

/*
* Assign fixed RAM addresses to facilitate a fixed MMU table.
* PHYS_MEM_IPC_VRING & PHYS_MEM_IPC_DATA MUST be together.
*/
/* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
#if defined (VAYU_DSP_1)
#define PHYS_MEM_IPC_VRING      0x99000000
#elif defined (VAYU_DSP_2)
#define PHYS_MEM_IPC_VRING      0x9F000000
#endif
#define PHYS_MEM_IOBUFS         0xBA300000

/*
* Sizes of the virtqueues (expressed in number of buffers supported,
* and must be power of 2)
*/
#define DSP_RPMSG_VQ0_SIZE 256
#define DSP_RPMSG_VQ1_SIZE 256

/* flip up bits whose indices represent features we support */
#define RPMSG_DSP_C0_FEATURES 1

struct my_resource_table {
struct resource_table base;

UInt32 offset[18]; /* Should match 'num' in actual definition */

    /* rpmsg vdev entry */
    struct fw_rsc_vdev rpmsg_vdev;
    struct fw_rsc_vdev_vring rpmsg_vring0;
    struct fw_rsc_vdev_vring rpmsg_vring1;

/* text carveout entry */
struct fw_rsc_carveout text_cout;

    /* data carveout entry */
    struct fw_rsc_carveout data_cout;
    /* heap carveout entry */
    struct fw_rsc_carveout heap_cout;

/* ipcdata carveout entry */
struct fw_rsc_carveout ipcdata_cout;

/* trace entry */
struct fw_rsc_trace trace;

/* devmem entry */
struct fw_rsc_devmem devmem0;

/* devmem entry */
struct fw_rsc_devmem devmem1;

/* devmem entry */
struct fw_rsc_devmem devmem2;

/* devmem entry */
struct fw_rsc_devmem devmem3;

/* devmem entry */
struct fw_rsc_devmem devmem4;

/* devmem entry */
struct fw_rsc_devmem devmem5;

/* devmem entry */
struct fw_rsc_devmem devmem6;

/* devmem entry */
struct fw_rsc_devmem devmem7;

/* devmem entry */
struct fw_rsc_devmem devmem8;

/* devmem entry */
struct fw_rsc_devmem devmem9;

/* devmem entry */
struct fw_rsc_devmem devmem10;

/* devmem entry */
struct fw_rsc_devmem devmem11;
};

extern char ti_trace_SysMin_Module_State_0_outbuf__A;
#define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A

#pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
#pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)

struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
    1,      /* we're the first version that implements this */
    18,     /* number of entries in the table */
    0, 0,   /* reserved, must be zero */
    /* offsets to entries */
    {
        offsetof(struct my_resource_table, rpmsg_vdev),
        offsetof(struct my_resource_table, text_cout),
        offsetof(struct my_resource_table, data_cout),
        offsetof(struct my_resource_table, heap_cout),
        offsetof(struct my_resource_table, ipcdata_cout),
        offsetof(struct my_resource_table, trace),
        offsetof(struct my_resource_table, devmem0),
        offsetof(struct my_resource_table, devmem1),
        offsetof(struct my_resource_table, devmem2),
        offsetof(struct my_resource_table, devmem3),
        offsetof(struct my_resource_table, devmem4),
        offsetof(struct my_resource_table, devmem5),
        offsetof(struct my_resource_table, devmem6),
        offsetof(struct my_resource_table, devmem7),
        offsetof(struct my_resource_table, devmem8),
        offsetof(struct my_resource_table, devmem9),
        offsetof(struct my_resource_table, devmem10),
        offsetof(struct my_resource_table, devmem11),
    },

    /* rpmsg vdev entry */
    {
        TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
        RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
        /* no config data */
    },
    /* the two vrings */
    { DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
    { DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },

    {
        TYPE_CARVEOUT,
        DSP_MEM_TEXT, 0,
        DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",
    },

    {
        TYPE_CARVEOUT,
        DSP_MEM_DATA, 0,
        DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
    },

    {
        TYPE_CARVEOUT,
        DSP_MEM_HEAP, 0,
        DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
    },

    {
        TYPE_CARVEOUT,
        DSP_MEM_IPC_DATA, 0,
        DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
    },

    {
        TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",
    },

    {
        TYPE_DEVMEM,
        DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
        DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
    },

    {
        TYPE_DEVMEM,
        DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,
        DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
    },

    {
        TYPE_DEVMEM,
        DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
        SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",
    },

    {
        TYPE_DEVMEM,
        DSP_TILER_MODE_2, L3_TILER_MODE_2,
        SZ_128M, 0, 0, "DSP_TILER_MODE_2",
    },

    {
        TYPE_DEVMEM,
        DSP_TILER_MODE_3, L3_TILER_MODE_3,
        SZ_128M, 0, 0, "DSP_TILER_MODE_3",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
        SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
        SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
        SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
        SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
        SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
        SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
    },

    {
        TYPE_DEVMEM,
        DSP_PERIPHERAL_ISS, L3_PERIPHERAL_ISS,
        SZ_256K, 0, 0, "DSP_PERIPHERAL_ISS",
    },
};

#endif /* __CUSTOM_RSC_TABLE_VAYU_DSP_H__ */

0 Ramprasad over 7 years ago in reply to user5163780

TI__Mastermind 30480 points

Hi,
TI has not tried loading dspdce firmware on DSP2 since few changes are required in kernel as well as dspdce also.
What is the reason for you trying this, can you let me know?

Please note that from PSDKLA3.04 onwards dspdce will be deprecated.

Ram

0 user5163780 over 7 years ago in reply to Ramprasad

Prodigy 40 points

we refer dspdce to porting our image algorithm to DSP1 and DSP2。

As you said, dspdce will be deprecated, then which example do you suggest to refer to transplant our image algorithm on DSP (DSP1 and DSP2) of J6?

0 Ramprasad over 7 years ago in reply to user5163780

TI__Mastermind 30480 points

Hi,
Yes dspdce is the only way to integrate xDAIS video/audio codecs running on DSP.
If you are planning both the DSPs to use image algorithms, how will the application differentiate between cores with same VIDEC API?

Processors

Processors forum

RTOS/DRA756: HOW can I load dspdce fireware on DSP2 of J6