Hi,
Related to the image attached to this post, I want to know main differences between Silicon Revision and CPU Revision.
Would you please give some examples to make it clear?
Thanks
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Hi,
Related to the image attached to this post, I want to know main differences between Silicon Revision and CPU Revision.
Would you please give some examples to make it clear?
Thanks
Hi,
The question I've asked here is related to differences between silicon revision and cpu revision. I have gotten the answer of my other question. But this another matter.
I want you to help me understand these revisions better. In the related application report written by Mugdha Gadkari & Peter Chung, it says:
"One important thing to note is that the silicon revision and CPU revisions are not same and in no way related."
I know that the silicon revisions are related to bug fixes and workarounds, butt deep down I really want to know differences.
Is there any book or article describing and discussing extensively these things?
Is there any book or article describing and discussing extensively these things?
Hi Hossein,
You are referring to this app note about CPU revisions and Silicon revisions: http://processors.wiki.ti.com/images/f/f4/C55x_CPU_revision.pdf
Compare the TMS320C55x DSP CPU Reference Guides for each CPU revision...
CPU 2.2: http://www.ti.com/lit/ug/spru371f/spru371f.pdf (available from the TMS320C5509A product page)
CPU 3.3: http://www.ti.com/lit/ug/swpu073e/swpu073e.pdf (available from the TMS320C5515 product page)
You will find from C55xx CPU Rev 2.2 to CPU Rev 3.3 improvements in...
* Data-read data bus BB width (16-bits to 32-bits), which allows higher dual-MAC performance (supports 4 independent operands instead of 3)
* Instruction Buffer Queue length increase from 64 Bytes to 128 Bytes (now supporting 64-bit parallel instructions instead of 48-bit)
* 3 23-bit address generation units (up from 16-bit)
* New instructions like LMS, LMSF, Parallel MACs with 4 operands, parallel stores - these allow speedups for 16-bit complex vector multiplies, 32-bit extended precision vector multiplies, 16-bit real vector multiplies, and 16-bit real vector dot products.
You might also refer to the respective Instruction Set Reference Guides for more details.
Additionally, the C55x core has many improvements over the C54x core like 2 MAC units instead of 1, 16-bit ALU in addition to 40-bit ALU, 24-bit extended addressing modes over 16-bit, additional instructions, protected instruction pipeline, etc.
Hope this help,
Mark
Hi,
Is there any fundamental and theoretical book related to these things?
Is there any scientific definition or standard in electronics about CPU revisions and Silicon revisions?