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66AK2H14: SOC in reset during power-up

Madhu Sharma
Expert 2915 points
Part Number: 66AK2H14


Hi,

In my design, I am using a CPLD for controlling the Reset signals of 66AK2H14 device.

In the datasheet, it is mentioned that prolonged reset after power-up will cause reliability issues.

After all the powers are up, the CPLD will take 100mS for its configuration. So the SOC will be out of reset only after 100mS of power-op.

Please let me know whether this 100mS delay is acceptable or will there be any chances of reliability issues.

Thanks & Regards,

Madhu

  • 0
    TI__Guru**** 161600 points
    Hi Madhu,

    The datasheet states:
    "The device should not be held in a reset for times exceeding one hour at a time and no more than 5% of the total lifetime for which the device is powered-up."

    100 milliseconds on power up should be fine. See this thread:
    e2e.ti.com/.../283225

    The problem comes when you hold the device for more than 1 hour in reset state.

    Best Regards,
    Yordan