Part Number: PROCESSOR-SDK-AM335X
Other Parts Discussed in Thread: AM3352
Tool/software: Linux
Hi, I'm trying to get my custom board with AM3352 processor (linux rt sdk 4.00.00.4) into UBOOT and I'm having some trouble getting mDDR working right.
My issue is that once I jump to u-boot (0x80800000), there's usually just garbage there (sometimes there's no branch instruction at 0x8080000, other times it is there, but the next few instructions aren't there), so I get some sort of exception due to the processor trying to execute that garbage.
I've used both the AM335x mDDR Timing Configuration Tool and RatioSeed_AM335x_boards spreadsheets (from here) to generate my timings, and I made some progress with that (initially I had no serial output), but when I look at the Memory Browser in CCS at addresses mapped to mDDR (0x80000000 to 0x8FFFFFFF) while using Continuous Refresh, I can see the data changing back and forth, leading me to believe that there is still a DDR configuration issue. I've tried both the optimized and relaxed values generated by the timing configuration tool, but neither fix my issue.
My mDDR chip is the MT46H128M16LF.
Currently, my serial output is this:
CCCCCCCC U-Boot SPL 2017.01-00319-geae4602-dirty (Nov 09 2017 - 10:59:03) Trying to boot from MMC1 spl: mmc boot mode: fs reading uboot.env ** Unable to read "uboot.env" from mmc0:1 ** Using default environment reading u-boot.img reading u-boot.img reading u-boot.img reading u-boot.img Jumping to U-Boot loaded - jumping to U-Boot...
I know the chip works because I can load Windows CE on it and it performs fine (I see no data changes in CCS), what confuses me even more is that when I take the values from windows and copy them to linux, I get no serial output on linux (DDR fails immediately).
These are my current register values (linux):
#define DDR_EMIF_READ_LATENCY 0x4 #define DDR_EMIF_TIM1 0x04447289 #define DDR_EMIF_TIM2 0x10160580 #define DDR_EMIF_TIM3 0x000000E7 #define DDR_EMIF_SDCFG 0x20044c23 #define DDR_EMIF_SDREF 0x00000618 //200MHz * 7.8us = 1560 = 0x618 #define DDR_ZQ_CFG 0x50074BE4 #define DDR_RATIO 0x80 #define DDR_INVERT_CLKOUT 0x0 #define DDR_RD_DQS 0x40 #define DDR_WR_DQS 0x0 #define DDR_PHY_FIFO_WE 0x110 #define DDR_PHY_WR_DATA 0x40 #define DDR_IOCTRL_VALUE 0x18B
And Windows CE 7:
#define CDS_EMIF_READ_LATENCY 0x4 #define CDS_EMIF_TIM1 0x04447289 #define CDS_EMIF_TIM2 0x101705c0 #define CDS_EMIF_TIM3 0x000000E7 #define CDS_EMIF_SDCFG 0x20004EA3 #define CDS_EMIF_SDREF 0x00000618 #define CDS_ZQ_CFG 0x50074BE4 #define CDS_RATIO 0x80 #define CDS_INVERT_CLKOUT 0x0 #define CDS_RD_DQS 0x40 #define CDS_WR_DQS 0x0 #define CDS_PHY_FIFO_WE 0x110 #define CDS_PHY_WR_DATA 0x40 #define CDS_IOCTRL_VALUE 0x18B
Am I missing some register that I need to set?
Any assistance would be greatly appreciated.
Thanks,
Kevin
