RTOS/AMIC110: EtherCAT Slave PHY issue

Hi Steven

Regretfully our knowledge on this phy is very limited.

A good source of information on Sitara processors is the Sitara FAQ http://processors.wiki.ti.com/index.php/FAQ_Sitara_Industrial

The FAQ lists a guide on information on porting industrial applications from a TI Sitara EVM to a custom board that is available at http://processors.wiki.ti.com/index.php/Industrial_SDK_EMAC_Porting_Guide

A debug guide is in development that is expected to be available by late December.

Beckhoff also has some recommendations in their phy selection guide and trouble shooting guide at https://www.beckhoff.com/english.asp?download/ethercat_development_products.htm

Can you provide more detail on what issues the customer is encountering?

David

David, 

Thanks for your feedback and providing the useful links! 

The problem is that when customer change to the KSZ phy, the EtherCAT communication would fail. Specifically, the EtherCAT link doesn't work correctly even the link light is on.  

After several days' debugging, it was found that the phy link has to be set established manually, then it could connect to the EtherCAT master. By adding the code of "while(bsp_pruss_mdio_phy_link_state(pruIcss1Handle, 1) != 2)" after phy initialization,  it could link normally.  However, without Ethercat cable plugged in, the code would stop waiting here.

Here comes the questions:

1. Does the PRU EtherCAT design requiring any special sequencing for the PHY? As the KSZ phy could work well with ET1100 (customers' previous design), but it cannot directly work with AMIC110. So customer is asking for the AMIC110 requirement about the PHY part, such as sequencing. 

2. They're curious about  some operation, so want to get the document about the below AMIC registers definition and operation/programming model. Can we provide the documents?

#define ESC_ADDR_TI_PORT0_ACTIVITY                  0xE00

#define ESC_ADDR_TI_PORT1_ACTIVITY                  0xE04

#define ESC_ADDR_TI_PORT0_PHYADDR                 0xE08

#define ESC_ADDR_TI_PORT1_PHYADDR                 0xE09

#define ESC_ADDR_TI_PDI_ISR_PINSEL                     0xE0A

#define ESC_ADDR_TI_PHY_LINK_POLARITY             0XE0C

#define ESC_ADDR_TI_PORT0_TX_START_DELAY    0xE10

#define ESC_ADDR_TI_PORT1_TX_START_DELAY    0xE12

#define ESC_ADDR_TI_ESC_RESET                           0xE14

PS: Here is an example for why the document is needed. 

Customer found that if they commented the below codes, the slave part cannot connect to the master normally. They want to learn what happen/operation is done here.

    //Indicate PHY address to firmware via vendor specfic registers

    bsp_write_byte(pruIcssHandle, pmdio_params->addr0, ESC_ADDR_TI_PORT0_PHYADDR);  //must done

    bsp_write_byte(pruIcssHandle, pmdio_params->addr1, ESC_ADDR_TI_PORT1_PHYADDR);

    bsp_write_byte(pruIcssHandle, (1 << PDI_ISR_EDIO_NUM),ESC_ADDR_TI_PDI_ISR_PINSEL);