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TMS320C6674: how to force PCIe to use posted writes in outbound direction

ti_andreas
Prodigy 100 points
Part Number: TMS320C6674

Hi,

I try to write some datawords from dsp on an fpga via Pcie.

Our fpga is only capable to receive pio reads and writes. Therefore i cannot burst the data.

When i write to the fpga every 32 bit word needs about 1.3 microseconds.

Therfore i expect that is a non posted transfer.

To enable posted write transfers, there is a bit in the pci CMD_STATUS register called POSTED_WR_EN, but is is marked as >>not applicable
for KeyStone device<<.

How can i activate this functionality in another way ?

Or is there any other possibility to force the pcie port to issue posted writes ?

Best regards

Andreas

  • 0
    TI__Guru 65405 points
    I've forwarded your query to the hardware design experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0
    Guru 13202 points
    Hello!
    Please let us know, how do you make your writes. If those are just stores, then PCIe works as expected. If you want to have multiword payload in your writes, you have to use DMA, either of DSP or FPGA side. Please take a look at e2e.ti.com/.../444356
  • 0 in reply to Victor Kazmirenko
    Prodigy 100 points
    Hi rrlagic,
    these are just stores. I dont want to have any bursts, so i dont setup a dma for the writes.
    Its just a 32 bit write from the cpu on a previosly mapped pcie address. This access works correctly but much slower then i would expect from a _posted_ write. So i assume its not posted and i seach for a way to get it posted.

    regards Andreas
  • 0 in reply to ti_andreas
    Guru 13202 points

    Hello,

    As long as your remote party is FPGA, you could setup some scoping, like ChipScope on Xilinx and peep into incoming TLPs on FPGA side. I bet you would see Type filed of 0_0000 meaning MWr, Memory Write Request. Those writes are posted by nature. I cannot imagine, what other type of TLP could be issued for memory write.

    Perhaps you are confusing posted nature of PCIe writes with CPU behaviour. You may think, that store to PCIe data window effectively puts data in some outbound buffer, whose capacity is limited. It takes time for PCIe subsystem to prepare headers and transmit your data word downstream.

    1.3 us per dword is somewhat slow too. It gives 32b/1.3e-6=24.6Mbps, or just 3MBps. I saw up to 45MBps with writes on x1 gen1 without bursts. We also don't know, whether you use 32 or 64 bit addressing. Nevertheless, you may estimate transaction layer overhead simply as payload/(overhead+payload), which for the simplest case of 32 bit addressing gives 3dword header, and transaction utilisation of 1/4. In 64 bit addressing that becomes 1/5 on transaction layer.

  • 0 in reply to Victor Kazmirenko
    Prodigy 100 points

    Hi - thanks for you quick response,

    my write are 64 bit addressed. I think the time for the transfer of one word is due to latency of the read side to get these data.

    There is a protocoll behind then fpga implementation so i had to fetch data from another source and this source slowed me down.

    I currently try to read my source in a burst and expect the data write rate to be similar to yours.

    I will report if its the way i expected.

    Thank you for your help

    best regards Andreas

  • 0 in reply to Victor Kazmirenko
    Prodigy 100 points
    Hi,

    the datarate of writing is now as expected. With a 5GBit link i got up to roughly 80MB/sec, so shurely posted writes are used.
    This rate is reduced when i send with 4 cores in parallel to different PCI destinations to 20MB/sec each.
    Thats a good value, considering the cores have to use the same PCIe interface.

    Again thanks for your help.

    Cheers Andreas