TDA2HG: PPLs and lock bits

Hi, Guillaume Hamard,

Please, re-attach the images. Now they can't be seen.

Regards,
Mariya

Just to add, the bit that controls the state, including LOCK state, is DPLL_EN bit, Each DPLL has its own register. For the registers name check Internal Clock Sources and Generators sub-chapter in TRM book.
Regards,
Mariya

Dear,

Thank you for the prompt answer.
Here below what we have for the TDA2E and TDA2H.

If i understood well, we should have a" Lock" bit for all DPPL listed (when cores are used).

For APLL_PCIE, [lease how we know if the PLL is lock or not before starting the software?
Thank you.



For TDA 2E:

• DPLL_MPU: It supplies the MPU subsystem clocking internally.
• DPLL_IVA: It feeds the IVA subsystem clocking.
• DPLL_CORE: It supplies all interface clocks and also few module functional clocks.
• DPLL_PER: It supplies several clock sources: a 192-MHz clock for the display functional clock, a
96-MHz functional clock to subsystems and peripherals.
• DPLL_ABE: It provides clocks to various modules within the device.
• DPLL_USB: It provides 960M clock for USB modules (USB1/2/3/4).
• DPLL_GMAC: It supplies several clocks for the Gigabit Ethernet Switch (GMAC_SW).
• DPLL_DSP: It feeds the DSP Subsystem clocking.
• DPLL_GPU: It supplies clock for the GPU Subsystem.
• DPLL_DDR: It generates clocks for the two External Memory Interface (EMIF) controllers and their
associated EMIF PHYs.
• DPLL_PCIE_REF: It provides reference clock for the APLL_PCIE in PCIE Subsystem.
• APLL_PCIE: It feeds clocks for the device Peripheral Component Interconnect Express (PCIe)
controllers.




TDA 2H:

DPLL_ABE
DPLL_CORE
DPLL_DEBUGSS
DPLL_DSP
DPLL_EVE
DPLL_GMAC
DPLL_HDMI
DPLL_IVA
DPLL_MPU
DPLL_PER
APLL_PCIE
DPLL_PCIE_REF
DPLL_SATA
DPLL_USB
DPLL_USB_OTG_SS
DPLL_VIDEO1
DPLL_VIDEO2
DPLL_DDR
DPLL_GPU

Best Regards