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Linux/DRA745: LCD clock frequency configuration problem

Cesar.Xi
Expert 1455 points

Part Number: DRA745

Tool/software: Linux

Hi,

kernel version：4.4.45

dtb: dra7-evm-lcd-osd.dtb

I found that it was wrong to calculate the clock frequency in  the dra7x-evm-lcd-osd.dtsi;

i calculate lcd clock:

clock-frequency =  ( hactive +  hfront-porch + hback-porch + hsync-len )  *  (vactive + vfront-porch + vback-porch + vsync-len ) * vertical_frequency

                          =  (1920+112+32+16 ) * (1200+16+16+2) * 60

                          =  2080 * 1234 * 60

                          = 154003200

the clock-frequency default configue as 154000000, the lcd can display, but i change the  clock-frequency to 154003200, the lcd screen is not displayed;

i'm confused,please help me.

 

thanks,

Cesar

       

  • 0
    TI__Mastermind 42515 points
    Hi Cesar,

    I have forwarded your question to DSS expert.

    Regards,
    Yordan
  • 0 in reply to Yordan Kamenov
    TI__Expert 5970 points

    Hi,

    I was able to reproduce your issue. With pixel clock changed to 1540032000, DSS kernel driver finds this mode to be invalid and does not initialize the LCD.

    Here is the relevant part from the kernel logs. You can obtain the same by adding drm.debug=0x4f to the kernel boot arguments.

    [    5.688969] [drm:drm_helper_probe_single_connector_modes_merge_bits] [CONNECTOR:36:Unknown-1]
    [    5.697552] [drm:omap_connector_get_modes] lcd_vout1
    [    5.702544] [drm:drm_mode_debug_printmodeline] Modeline 41:"1920x1200" 0 154003 1920 2032 2048 2080 1200 1216 1218 1234 0x48 0x1500000a
    [    5.714802] [drm:drm_mode_prune_invalid] Not using 1920x1200 mode: VIRTUAL_Y

    The existing timings in the device tree file are standard for the 1920x1200 reduced blanking mode. You can check the same with "cvt" command on ubuntu.

    $ cvt -v -r 1920 1200
    # 1920x1200 59.95 Hz (CVT 2.30MA-R) hsync: 74.04 kHz; pclk: 154.00 MHz
    Modeline "1920x1200R"  154.00  1920 1968 2000 2080  1200 1203 1209 1235 +hsync -vsync

    You can also refer to the below sheet for pixel clock calculations.

    regards,

    Venkat

  • 0 in reply to Venkat Mandela
    TI__Expert 5970 points
    Hi,

    DSS is finding this mode to be invalid because the configured pixel clock (154003200) cannot be generated within the Video PLL.

    regards,
    Venkat
  • 0 in reply to Venkat Mandela
    Expert 1455 points
    Hi,

    thank you for your reply.

    regards,
    Cesar