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TMDSEVM572X: Design notes clarification

Laura Manley
Prodigy 150 points

Part Number: TMDSEVM572X
Other Parts Discussed in Thread: TPS659037, TMDXIDK5718

This question is in reference to the TI_AM572XEVM_REV_A3a.PrjPcb schematic. I am removing the power on/off switch (S1) using the design notes here: https://e2e.ti.com/support/applications/automotive/w/design_notes/3266.should-i-use-powerhold-or-pwron-to-turn-on-the-pmic,

Quoting from the design note, "A second option is to tie POWERHOLD high permanently (eg. to LDOVRTC_OUT), and connect a powergood or supervisor reset to RESET_OUT.  Either of these configurations allow the system to turn on when power is supplied, and will disable the PMIC before power is lost to ensure the processor's power-down sequence is still met."

I deleted the switch and left PWRON (ball G8) unconeected. POWERHOLD is tied to LDOVRTC_OUT; my question is about connecting a powergood or supervisor reset to RESET_OUT. On the rev A3a schematic, PMIC_RESET_OUT is already connected to a NOR gate on page 8, of which the output signal RTSOUTn is tied to the eMMC on page 18. Is this already sufficient to trigger the proper power down sequence when power is removed from the board?

  • 0
    TI__Guru**** 393215 points
    The factory team have been notified. They will respond here.
  • 0
    TI__Genius 13567 points

    Hi Laura,

    Looks like I need to track down whoever wrote that FAQ to get it updated. Connecting a voltage supervisor to the RESET_OUT does not do anything is not ideal. Whether you use a pre-regulator PG output or you create your own PG output with a voltage supervisor - it should connect to the POWERHOLD pin.

    The TPS659037 datasheet has a section 5.4.1 that explains the embedded power controller state machine which I recommend becoming familiar with. There are details that cover what it considers an "OFF2ACT" or an "ACT2OFF" request.

  • 0 in reply to Ahmad_Rashed
    Prodigy 150 points

    I picked out an active-high TI voltage supervisor: TLV810MDBZR and connected VDD to 3.3V and the RESET output is connected to PMIC POWERHOLD. Does this look like a good choice, or are there other pitfalls I need to look out for?

  • 0 in reply to Laura Manley
    TI__Genius 13567 points

    So you are designing to survive unexpected power removal: The power down sequence takes a little over 1 millisecond on the TPS659037 so you want to make sure you have enough capacitive energy at the PMIC to last 1 ms. This is why our IDK and our GP EVM have input diodes and 100uF capacitors on the input supplies. See the attached image for a block diagram of the idea. U105 on the TMDXIDK5718 schematic page 5 is set up this way.