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Omap3530 TLV320AIC3104 McBSP4 Rx sync errors

Andy Clayton
Intellectual 390 points
Other Parts Discussed in Thread: OMAP3530, TLV320AIC3104, TPS65930

I am currently working on a design which uses an Omap3530 and a TLV320AIC3104 codec. The Omap is configured as the master and the codec is configured as the slave device. The 256fs clock is generated from the TPS65930 device and distributed to CLKS on the Omap and to the codec.

What we are seeing are RX sync errors when we are recording audio - could this be a problem caused by the 256fs clock being sourced from the TPS65930 device. Would it be better to use the internal 96MHz clock in the Omap and have the Codec regenerate the sample clock from the bit clock using it's internal PLL?

As the codec has a 1V8 IO voltage there is no level translation on the board so the I2S signals connect straight through. The data format is 16bit 44.1KHz, so we have a dual-phase frame ( 16 bits in each frame) with the 256fs clock running at 11.2896MHz and the bit clock running at 1.4112MHz. As the Omap actually generates the frame sync I am a bit lost as to how it can get RX sync errors.

Any help would be appreciated.

 

Andy

 

  • 0
    TI__Mastermind 28045 points

    Your setup should work just fine.

     

    Things to check…

     

    1)    The clock from the McBSP is clean and has no noise or reflections. The clock should have a series termination resistor close to the McBSP.TXCLK pin

    2)    The received data/sync is captured on the opposite clock edge that that used for transmission.  

    3)    FSR programming is the same for the receiver as the transmitter.  

      

    Paul

  • 0 in reply to PaulM
    Intellectual 390 points

    Paul,

     

    The McBSP clock is clean and stable ( there is no series resister though). The received data/sync is captured on the opposite edge to that used for the transmission ( we have tried it both ways), and the FSR is the same for the receiver as the transmitter ( again we have tried this both ways) and we still get the same result - everything we do results in RX frame sync errors and bad quality audio being recorded.

    We had this problem with a previous board if you recall and it was seemed to be solved by using a different level translator although with hindsight that must have been a coincidence as this problem is very very similar.

    What can cause the RX sync error? we have checked the sync, data clock and 256fs clock and they are all clean and stable.

    There is a delay from the rising edge of the clk256fs clock ( CLKS) and the edges of the data clock and frame sync of around 0.25us would that cause a problem - if so that delay is introduced internel to the Omap, so a bit difficult to sort out.

     

    Andy

  • 0 in reply to Andy Clayton
    TI__Mastermind 28045 points

    Andy

    The RX Frame Sync Error is generated when a frame sync is generated too early, ie before the previous frame has completed.

    For example, If a frame is 64 bits The the FPER is set to 63. The frame sync pulse for I2S mode should be set to half the frame period (32) giving a FWID of 31. If a new FS is generated within the 64 clock cycles of the previous FS then the error will be generated.  See section 21.4.4.3 of the latest TRM for a full description (http://focus.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=spruf98i&fileType=pdf)

    The clock delay from clk256fs to  the McBSP CLKX should have no impact as everything should be timed relative to the CLKX signal connected between the OMAP and the TPS devices.

    What about glitches/noise on FSX?

    If you put a scope on the clk and FSX signal do you see the correct FSX period?

      Paul

  • 0 in reply to PaulM
    Intellectual 390 points

    Paul,

     

    No glitches/noise on FSX or the clk - verified by the scope and the FSX period is correct 44.1KHz and you can clearly see the 16 data clock cycles in every phase.

     

    The errata on the TPS65930 device mentions "synchronisation problems" when the TPS65930 device generates the 256fs clock and the Omap is the master and recommends a 33R series resister ( which we have) to minimize reflection problems.Could this be a problem?

    We are currently working on a driver that does not use the 256fs clock from the TPS65930 but uses the Omap internal 96MHz clock to generate the data clock and frame sync and the internal Codec PLL to basically reconstruct the 256fs clock from the data clock. If nothing else at least it will narrow the search down to 3 lines!!!

     

  • 0 in reply to Andy Clayton
    TI__Mastermind 28045 points

    The errata fro the TPS65930 could well be a problem resulting in corrupt data, but I fail to see how it would manifiest as a FS error especially since you see the correct bit times on the waveforms. The MCBSP receiver sees the same clock and FS as you see so  the receiver would have to skip a clock cycle to to think that the FS was coming early.

    You could try the Digital Loop Back mode and see if you still have sync errors. This will wrap around the the DX to DR and isolate the clk and FS from the pins.   

    Is ther any clue in the corrupted data? Are only some bits corrupted, double samples,

    Do you get a FS error fro every word?

      Paul

  • 0 in reply to PaulM
    Intellectual 390 points

    Paul,

     

    We managed to get it to work correctly without sync errors by making the Omap the slave and the Codec the master -  nothing else changed. Why would that make a difference? I know that is how it works when the TPS65930 is the codec but surely the Omap is capable of being the master device.

     

    This is fine in this situation as the codec allows for it to be the master, but we would like to understand what causes this, as in the future we may have to use a codec that does not allow for it to be the master.

     

    Andy

  • 0 in reply to Andy Clayton
    TI__Mastermind 28045 points

    Andy

    Good to hear that you have a solution for now.

    Can you answer the following so that I might try and understand the problem...

    Did setting the DLB mode eliminate the sync errors?
    Were the SYNC errors on every frame, every X frames, or random?
    Do you still see the error if using the internal 96MHz clock? If yes, what about if the TLV device is disconnected form the McBSP (if possible)?
    Can you share your register settings?

      Paul

     

     

  • 0 in reply to PaulM
    Intellectual 390 points

    Paul,

     

    Setting DLB mode did not eliminate the sync errors - although it did make the problem a little bit better.

     

    In DLB mode no they seem to come in batches. In other modes they were pretty much constant.

     

    Yes we still got the errors while using the 96MHz internal clock ( the codec regenerated the 256fs clock from the data clock). We also disconnected the frame sync from the codec and we still get the errors.

     

    Here's a dump - we have pretty much tried every format that the Omap can do.

     

    REGS: c041a788, PCR0 = 0x00000f00, SRGR2 = 0x00001000
    omap_mcbsp_dai_set_dai_fmt.473 - PCR0: 0x00000f0f, RCR1: 0x00000000, RCR2: 0x00000001, XCR1: 0x00000000, XCR2: 0x00000001
    SRGR1: 0x00000000, SRGR2: 0x00001000
    omap_mcbsp_dai_set_dai_sysclk.617 - PCR0: 0x00000f0f, RCR1: 0x00000000, RCR2: 0x00000001, XCR1: 0x00000000, XCR2: 0x00000001
    SRGR1: 0x00000007, SRGR2: 0x00001000
    ---------- aic3x_hw_params.774
    ### aic3x_write(reg=9) = 0x00
    aic3x_hw_params - sysclk = 11289600
    ---------- aic3x_hw_params.805
    ---------- aic3x_hw_params.807
    ### aic3x_write(reg=3) = 0x10
    ### aic3x_write(reg=101) = 0x01
    ### aic3x_write(reg=3) = 0x10
    ### aic3x_write(reg=7) = 0x8a
    ### aic3x_write(reg=2) = 0x00
    omap_mcbsp_dai_hw_params: framesize=32, freq: 11289600, div: 8, rate: 44100
    omap_mcbsp_dai_hw_params.372 - PCR0: 0x00000f0f, RCR1: 0x00000040, RCR2: 0x00008041, XCR1: 0x00000040, XCR2: 0x00008041
    SRGR1: 0x00000f07, SRGR2: 0x0000101f
    ### aic3x_write(reg=19) = 0x04
    ### aic3x_write(reg=22) = 0x04
    ### aic3x_write(reg=43) = 0x2f
    ### aic3x_write(reg=44) = 0x2f
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    omap-mcbsp omap-mcbsp.4: RX Frame Sync Error! : 0x39
    Aborted by signal Interrupt...### aic3x_write(reg=19) = 0x00

    ### aic3x_write(reg=22) = 0x00

     

    Andy

     

     

     

     

     

  • 0 in reply to Andy Clayton
    TI__Mastermind 28045 points

    Andy

    Thanks for the information.

    I'll see if I can replicate the problem on my board using the internal 96MHz clock and DLB mode when I get back to the office on the 27th.

     Paul

  • 0 in reply to PaulM
    TI__Mastermind 28045 points

    Andy

    I've tried your settings and several variations (DLB enabled, physical connection between DX and DR, etc) and have not yet seen any rxsync errors.

      Paul

  • 0 in reply to PaulM
    Intellectual 390 points

    Paul,

     

    Are you using the TPS65930 as the source of the main 256fs clock? or do you have a seperate crystal/oscillator in the system?

     

    Andy

  • 0 in reply to Andy Clayton
    TI__Mastermind 28045 points

    Andy

    I used the internal 96MHz with DLB enabled since this was simple to replicate on our EVM.

    Paul

  • 0 in reply to PaulM
    Intellectual 390 points

    Paul,

     

    I think that may be where out problem is. We were using the TPS65930 to generate the 256fs clocks which was then used by the Omap (master) and the Codec (slave), do you think that is a possibility.

  • 0 in reply to Andy Clayton
    TI__Mastermind 28045 points

    Andy

    I don't see how unless the clocks source is noisy - but as previously discussed that's not the case.

    What's strange is that you are also seeing the errors reported when using the internal clock with DLB mode. Since I can't reproduce the errors in the same mode there must be some other factor at play. Are your power supply voltages ok?    

    Is your software that run the internal clock/DLB test portable enough for me to try here?

      Paul