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TDA2Ex DDR3L Reset

Javier Jimenez80
Intellectual 390 points

Hi all,

Looking on Micron DDR3L memory datasheet, there is a parameter called tRPS that defines that a reset pulse must be between 0 < t < 200 ms after Vdd is stable (RESET# LOW to power supplies stable).

On the testbench I have measured that this pulse it's 250 ms, out of spec.

My question is: There is a register on the TDA that allows me to control ddr1_rst pulse?

Thanks.

Best Regards.

  • 0
    TI__Mastermind 42515 points
    Hi Javier,

    I have forwarded your question to a DDR expert.

    Regards,
    Yordan
  • 0
    TI__Mastermind 38590 points

    Hi,

    No, there is no such register to control the ddr1_rst pulse.

    Also, can you ask the memory supplier for clarification on this parameter? RESET# should be asserted (driven low) for much longer than 200 ms after VDD is stable. As an example, the following text is taken from JESD79-3F, which states that RESET# needs to be maintained for a minimum of 200 us with stable power.

    3.3 RESET and Initialization Procedure

    3.3.1 Power-up Initialization Sequence

    The following sequence is required for POWER UP and Initialization.

    1. Apply power (RESET# is recommended to be maintained below 0.2 x VDD; all other inputs may be

    undefined). RESET# needs to be maintained for minimum 200 us with stable power.

    Best regards,
    Kevin

  • 0 in reply to Kevin S
    TI__Prodigy 420 points

    Javier,

    I believe tRPSmax=200ms indicates that the voltage ramp time between 300 mv to VDDmin must be no greater than 200 ms and it is required that reset pin to the DDR device is held LOW while the power is ramping up. You will see RESET pin remaining low while the supplies are ramping and until SW triggers DDR initialization sequence. There is no max limit as to how long the reset can stay low.

    Please check if the supply ramp time is >200ms. If yes, that a violation.

    Best Regards

    Rajesh Veettil

  • 0 in reply to Rajesh Veettil36
    Intellectual 390 points
    I think that the parameter that you are talking about it is called tVDDPR (Begin power supply ramp to power supplies stable).

    Thanks.
    B.R.
  • 0 in reply to Javier Jimenez80
    TI__Prodigy 420 points

    Hi Javier,

    Please get clarification on tRPS parameter from the memory vendor. I don't think that's a parameter defined in the DDR3 JEDEC spec as far as I know. 

    BR

    Rajesh Veettil.