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RTOS/AM4377: Cache configuration question

Part Number: AM4377
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Hi Team, 

My customer recently met an issue with the MMU cache setting. The device is AM4377, while the software is using the processors sdk RTOS. 

During their RTOS application, MMU has to be used for performance improvement.. However, there seems to be two ways to configure the MMU in the RTOS:

1. Modify the project’s .cfg file.

Refer to the example under  C:\ti\pdk_am437x_1_0_8\packages\MyExampleProjects\UART_BasicExample_idkAM437x_armExampleProject , the Cache and MMU configuration part in the am437x_app_idkam437x.cfg settings. like below:

2. Adding the codes in the project main.c file.  

Refer to the example under C:\ti\pdk_am437x_1_0_8\packages\MyExampleProjects\EMAC_BasicExample_idkAM437x_armBiosExampleProject, the SDKMMUInit function in main_idkAM437x.c file of the project 

What's the difference between these two configuration? Is there any document telling the configuration steps?

My customer feedback that the result is so different if they configure the MMU in each way. 

In addition, is there any document telling the different effect of the MMU setting as below? This settings seems to affect a lot to the external device operation delay and the time that consumed for reading data from DDR. 

My customer is now dealing with an issue that the DDR data read is very consuming after the MMU initialization. They want to figure out how each configuration as below affects the DDR data read latency. 

  • The RTOS team have been notified. They will respond here.
  • Hi Steven,

    There maybe some difference affecting the performance with different ways of setting MMU, as the two ways you mentioned. The setting in SYSBIOS .cfg will be overwritten by the SDKMMUInit () in the code. One of my colleagues is working on a demo for a peripheral access latency.

    For DDR access, can you try the setting in .cfg with below to see if any help?

    Mmu.initDescAttrsMeta(attrs1);
    attrs1.type = Mmu.DescriptorType_BLOCK; /* BLOCK descriptor */
    attrs1.shareable = 2; /* Sharerable */
    attrs1.attrIndx = 2; /* Cached, normal memory */

    /* Set the descriptor for each entry in the address range */
    for (var i=0x80000000; i < DDR_endaddress; i = i + 0x00200000) {
    /* Each 'BLOCK' descriptor entry spans a 2MB address range */
    Mmu.setSecondLevelDescMeta(i, i, attrs1);
    }

    Regards, Eric
  • Hi,

    I add your mmu initial code to my project .cfg, but the CCS complier can't find 'initDescAttrsMeta'. The version of CCS is 7.2

    In addition, if the setting of DDR is Sharerable, the access speed is improved. But, the result of ADC EDMA transmission is not updated. If I set the attribute of mmu ‘0’ ,the result of ADC EDMA transmission is ok.

    The question confused me…