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RTOS/TDA2EXEVM: MCASP

Part Number: TDA2EXEVM


Tool/software: TI-RTOS

Hi,

I had gone through an example mcasp_transmit_tda2xx.c in drv > stw_lld. I wanted to test this example. I tried compiling the examples alone, i couldn't get the binary of that particular example. After that i changed the makefile stw_examples_component.mk, for that particular example i added ipu1_0 to its corelist, after which that example got compiled.

Right now, when i m testing that example, what i see in the log is just junk values.

TDA2xx SBL Boot

 DPLL Configuration Completed

 Clock Domain Configuration Completed

 Module Enable Configuration Completed

 TI EVM PAD Config Completed

 DDR Config Completed

 App Image Download Begins

 SD Boot - file open completed successfully

Trying to boot App Image with header version 1

 IPU1 CPU0 Image Load Completed

 App Image Download Completed

 Putting MPU CPU1 in Off mode

 EVE MMU configuration completed

 EVE MMU configuration c�leted

EVE M
     MU cMocnfigurAaStion completed
P
p EVE MM US iconnfigeurtatioonn comep letaed
lp
 *i**c**a*t*********i*o******n** *****************************************

 PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles

 SBL Initial Config Cycles - 144657  (12.34 ms)
 SOC Init Cycles - 170604  (14.55 ms)
 DDR Config Clock Cycles - 43685  (3.72 ms)
 App Image Load Cycles - 494749  (42.21 ms)
 Slave Core Bootup Cycles - 229311  (19.56 ms)
 SBL Boot-up Cycles - 1084064  (92.50 ms)
 Time at which SBL started IPU1_0 - 11457  (0.97 ms)
***************************
    *** *i**2**c*** *w******r*******i**t

 Peutting MPU in Retenti:on...
   address :  0x0  data :  0x0
I2c write successful
GPIO Expander configured �
 

can u please help me through this.

  • Hi,

    McASP transmit example is part of csl repo at csl\example\mcasp\mcasp_transmit

    For tda2xx devices the example is built for a15 core, you can build specifying the CORE=a15_0 option.

    The junk charectors you are seeing are because you are running using SBL and the IPU core starts running before the SBL running on A15 core finishes its execution. there are some prints on UART by SBL after IPU starts running.

    You can put a delay in the beginning if you want to run the example from IPU1.

    You can refer the csl user guide for the example description and expected output. You should probe the McASP lines.

    Regards,
    Prasad