Part Number: AM5K2E04
Tool/software: Linux
Hi!
Our system consists of an AM5K2E04 chip and a Xilinx FPGA chip. They are connected by PCIE.
I used XPDMA IP core (which has a PCIE core and a DMA core) in FPGA, and also installed the proper PCIE driver provided by Xilinx.
I can use ARM to access the PCIE register and DMA register in FPGA successfully, that means that I can do both cfg access and memory access correctly, in the outbound direction.
But the DMA core in FPGA need the PCIE core in FPGA to be a master, which means AM5K2E04 PCIE should be able to work in the inbound direction.
Here is the problem:
1. When I start Linux OS with PCIE RC mode, only BAR0 is configured, and BAR1 is disabled.
2. When I install the PCIE driver provided by Xilinx, BAR1 is not enabled either.
3. When I enable BAR1 with the instruction in the PCIE user guide, access started by FPGA does not work.
4. When I check the PCIE register in FPGA, it says that there is a CRC error.
Should BAR1 be disabled due to the default configuration of Linux OS?
How can I use the driver correctly and which register should I configure for the inbound access ?
Thank you very much!
