• State Answer Suggested
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 98 subscribers
  • Views 516 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C6474 Booting process

bala ganapathy
Prodigy 130 points
Other Parts Discussed in Thread: CCSTUDIO

Hi

I am using C6474 EVM (Mezzanine board).

In EVM board, I am seeing Four EEPROMs

1. I2C Factory Boot configuration EEPROM.

2. I2C User Boot configuration EEPROM.

3. I2C Boot EEPROM for Each C6474 DSPs.

I am designing the c6474 board for my application,

 Can u please tell whether the Factory Configuration EEPROM is must for booting?

if so, How can i get the Factory configuration EEPROM?   

Also, Can u please tell how to program the "I2C User Boot configuration EEPROM"? 

 

Thanks,

Bala

  • 0
    Expert 1070 points

    Hi Bala,

    It's strangely satisfactory to see I'm not the only one who stumbled over this. It took me some time to figure this out, but this is what I found:


    EEPROMs on the EVMC6474:

    • User EEPROM CAT24C256WI (256kbit, address 0x52).
    • Factory EEPROM CAT24C256WI (256kbit, address 0x51).
    • AT24C1024W (1Mbit, 0x50) hooked up to both the C6474s directly (according to the datasheet). In reality the stuffed part is a CAT24C256WI, just like all the other EEPROMs

    The CPLD and CPU1 I2C bus are hooked up together. The CPU2 I2C bus is isolated, so it has no access to User and Factory EEPROMs.

    User EEPROM and Factory  EEPROM

    The User EEPROM and Factory  EEPROM contain settings for the CPLD, which controls the bootmodes on the C6474s by asserting IOs and also performs configuration of clocks and clock buffers on the board. Check page 2-7, Paragraph "2.6  I2C Boot Configuration EEPROM" for more info on the CPLD.


    C6474 booting

    The actual program executed on the processors after they come out of reset is stored in the Boot EEPROMs (I2C address 0x50), NOT the configuration EEPROM. This is because by default, the I2C Master Boot A is selected (I2C address 0x50) by the CPLD. There is an override option on the board, SW5.  When switched ON, SW_OVERRIDE causes the CPLD to use EEPROM to configure the C6474 bootmodes and board clocks , when OFF, it uses the SW5 settings. Really a name like “SW_EE_CONFIG” would have been more appropriate... The ON and OFF positions for SW5 have been reversed (for all other switch functions this seems to be the case as well).

    So, this is how it works:

    • The CPLD boots, C6474s are help in reset and are also unpowered since these variables are controlled by the CPLD.
    • CPLD reads settings for Clock chips and IOs to the C6474 Config IOs from either Factory or User EEPROM (Overriden by the switch if set to)
    • Dev num is also transferred thru GPIO. Here’s more info on the DEVCFG and CFG[3:0] pins:
    • (At default settings) The C6474s boot from Boot EEPROM (I2C address 0x50).

    Modifying the CPLD config EEPROM (Factory EEPROM  & User EEPROM):

    Spectrum Digital provides projects to read and write CPLD config EEPROM (User & Factory) on the development CD (After Installation they reside here: “C:\CCStudio_v3.3\boards\evmc6474_v1\tests\cfginfo” and “C:\CCStudio_v3.3\boards\evmc6474_v1\tests\usereeprom”)

    Modifying the C6474 Boot EEPROM (for CPU 1 & 2):

    Spectrum Digital provides a project boot.prj in “C:\CCStudio_v3.3\boards\evmc6474_v1\firmware\booteeprom”. The following description is supplied:

    This application puts the factory boot image into the I2C Boot EEPROM.  It includes a lock to prevent accidental overwriting of the factory image.  To run this application, you must open a memory window and write the magic number value 0xABCD1234 to address 0x00807FFCbefore running the program. Since the board has two cores, you need to run the program once on each core to program both EEPROMS.

    The program writes to EEPROM 0x50, which is the Core dedicated EEPROM containing the actual program. The whole idea with this program is that the main function is always executed by the bootloader (I2C Master Boot A mode). If a memory location in L2 (0x00807FFC) does not contain a magic value (0xABCD1234) , the LEDs are flashed in sequence (this is what you currently see when you power up the board). If it does, then the boot-image is written as stored in the program. That way, if you manually load the boot program, you can set the magic number with the debugger and flash your own bootloader.

    The tables written to specific addresses in EEPROM like “boot_param_config[]” contains values the I2C Boot loader, described op page 42 of the document: “SPRUEC6D: TMS320C645x/C647x Bootloader”.


    I hope this gets you going. For me the key issue was to realize that the Factory and User EEPROM are only accessed by the CPLD to set it's configuration. The actual porgram which flashes the LEDs sequentilly when you power your board resides in the Boot EEPROM (I2C address 0x50). With the Example programs it becomes much easier.

    We ended up deciding to use the EMAC bootloader which uses BOOTP (in gigabit mode only) or SRIO. An alternative would be to first boot from EEPROM (using I2C Master mode) which contains a secondary bootloader. The reason here is because there is limited space in the Boot EEPROMS (256kb...). An additional advantage is that with the secondary bootloader you can do whatever you please and even boot using McBSP or the AIF if you were inclined to.

    Regards,

    -Dirk