Linux/66AK2E02: baud rate for UART boot mode is not 115200

sathish v

Part Number: 66AK2E02

Tool/software: Linux

Hi,

We are trying to boot u-boot in our custom k2e board using UART boot mode. From the quick start guide, to use UART boot mode, we have to set the boot mode pin [1,2,3] to '111' .Once this is set, and port 0 is selected in bootmode pin 12, according to the guide we should see Character 'C' in the UART 0 console connected to PC with baud rate 115200 with no parity check and one stop bit. But we were not able to get the 'C' character, but some unknown character was printed. So we suspected the baud rate and probed the UART tx. By analysing the waveform, the data was send with baud rate 74400. Why K2 is sending the data with reduced baud rate? Are we missing some more boot configuration?

Regards,

Sathish

over 8 years ago

0 Cvetolin Shulev-XID over 8 years ago

TI__Guru 65405 points

Hi Sathish,

Thank you for your interest in our devices. I’ll need some time to gather data in the lab. Please allow me a few days and I’ll get back to you

BR
Tsvetolin Shulev

0 Michael Erdahl over 8 years ago

TI__Genius 13515 points

Sathish,

Please make sure your PLL is configured correctly on the bootmode pins (bootmode[7:5]). Verify your settings against section 9.1.4 System PLL Settings, and table 9-25 of the datasheet (http://www.ti.com/lit/ds/symlink/66ak2e02.pdf

Regards,
Mike

0 sathish v over 8 years ago in reply to Michael Erdahl

Intellectual 520 points

Hi mike,

Thank you for your reply mike. I verified the PLL setting in the bootmode[7:5]. We are setting them to 0b000. How this will decide the UART 0 baud rate? How to correctly configure the bootmode pins for the correct working of UART boot mode for the baud rate 115200?

0 Rex Chang over 8 years ago in reply to sathish v

TI__Guru 50170 points

Hi, Sathish,

I'll need some time to take a look at this on TI EVM.

Rex

0 sathish v over 8 years ago in reply to Rex Chang

Intellectual 520 points

sure rex. thank you for your help.

regards,

sathish

0 Bill Taboada over 8 years ago in reply to sathish v

TI__Mastermind 42545 points

Hi Sathish,
The UART baud rate is derived from the system clock. What is the frequency at the CORECLKP/N pins? If you have access to the SYSCLKOUT pin, could you measure the frequency at that point? That will let us know if the Main PLL is configured correctly and the frequency of the clock used as a source for the UART subsystem.
Thanks, Bill

0 sathish v over 8 years ago in reply to Bill Taboada

Intellectual 520 points

hi bill,
Core clock input is 100 MHz. I will try to probe the SYSCLKOUT Pin if possible.

0 Mukul Bhatnagar over 8 years ago in reply to Bill Taboada

TI__Guru* 85295 points

Hi Sathish
To help address Bill's query, you may also find the following clocking spreadsheet useful, to input your configuration and double check UART settings

www.ti.com/.../sprac72.pdf

Regards
Mukul

0 Bill Taboada over 8 years ago in reply to Bill Taboada

TI__Mastermind 42545 points

Hi Sathish,
Bootmode pins 7:5 are used to defined the PLL settings for UART boot specifically for the clock frequency at the CORECLKP/N clock input. You can find the PLL settings defined in Table 9-25 of the data manual. If you are setting these bits to 0b000, the boot code is expecting a CORECLK of 50 MHz. If you are using a different frequency for the CORECLK, the system clock will not be the frequency expected by the boot code and the UART baud rate will not be correct. That is why I am asking for the frequency of the clock at the CORECLK pins and the frequency at SYSCLKOUT. If you are using 100MHz then these bits should be set to 0b011.
Regards, Bill

0 sathish v over 8 years ago in reply to Bill Taboada

Intellectual 520 points

ok. Thanks for that suggestion bill. But I do tried by keeping the bootmode[7:5] to 0b011, which is the setting for 100MHz. still I got the same result.

0 Bill Taboada over 8 years ago in reply to sathish v

TI__Mastermind 42545 points

Hi Sathish,
Let me check on one thing that is confusing in the K2 documentation. The bits 7:5 refer to the bit position found in the DEVSTAT registers. As stated in the data manual BOOTMODE[15:0] in the K2E pin map associate with DEVSTAT register bits [16:1]. Based on this the BOOTMODE[6:4] should be set to 0b011, BOOTMODE3 set to 0b0 and BOOTMODE[2:0] set to 0b111 for proper UART boot with 100MHz reference clock. Is that what you have?
Regards, Bill

0 sathish v over 8 years ago in reply to Bill Taboada

Intellectual 520 points

yes correct bill. except one thing. bootmod3 is set to 0b1. If I set this to 0b0, then I'm not getting any data in UART0

0 Bill Taboada over 8 years ago in reply to sathish v

TI__Mastermind 42545 points

Hi Sathish,
What is the setting for the rest of the BOOTMODE pins? Settting the min pin to 0b1 will using a preconfigured setting and ignore the rest of the BOOTMODE pins. You may possible have an incorrect setting on one of those pins. Can you connect and emulator and read the DEVSTAT register? That will give use the BOOTMODE values latched by the SoC when it exits reset.
Regards, Bill

0 sathish v over 8 years ago in reply to Bill Taboada

Intellectual 520 points

All the other pins are configured as 0. I have a emulator. I will try to read the DEVSTAT REGISTER once get back to my office on monday. I think that should give us some insight. thank you bill.

0 Bill Taboada over 8 years ago in reply to sathish v

TI__Mastermind 42545 points

Hi Sathish,
The contents of the DEVSTAT register and the frequency of the SYSCLKOUT pin will go a long way to isolating the issue. I will check back on Monday morning for your reply.
Regards, Bill

0 sathish v over 8 years ago in reply to Bill Taboada

Intellectual 520 points

Hi bill,
I think setting the min bit in BOOTMODE register was the problem. I set that to 0b0 and set the PLL CONFIG to 0b011 (100MHz), It worked. This is little bit confusing, because with min bit set, SPI boot was working fine, So we thought it will work for UART too. Thank you the great help bill.

0 Bill Taboada over 8 years ago in reply to sathish v

TI__Mastermind 42545 points

Hi Sathish,

I am glad this solved your problem. If you check Table 9-14, you will see that the MIN bit selects the table values labeled default. The default value for the SYS PLL Setting is 4, which equates to a 156.25MHz CORECLK frequency in table 9-25. Since you are using a 100MHz clock input, the clock into the UART subsystem will not match the frequency expected and your baud rate will not be correct. The SPI boot doesn't configure the PLL so that problem would not be observed when using that boot mode. I'm glad I was able to help.

Regards, Bill

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Linux/66AK2E02: baud rate for UART boot mode is not 115200