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C6455 EMIF / C5510 HPI - master/slave race condition

dewilso4
Expert 1215 points

I'm using C6455 EMIF to connect to a C5510 HPI.  All data transfer's working great, but I'm running into a race condition which I can't seem to figure out how to solve.  

Here's the setup: I've got a couple of ring buffers on both the C6455 and C5510 as well as a couple of memory locations which I access from both chips.  99% of the time (actually, more like 6 nines), everything works fine, but occasionally from the C6455 I attempt to write to a memory location on the C5510 while the C5510 is also trying to write to that same memory location.  Of course bad things happen, and the resultant value at that memory location becomes incorrect.

My question is: Is there any way of preventing something like this?  The standard LCK or semaphore techniques obviously won't work because of the data residing on two different chips.  I'm trying to come up with some smart way of eliminating this race condition, maybe something like a write and verify on the C5510 (but with less expense).  Any suggestions would be appreciated!

  • 0
    TI__Expert 6991 points

    Derek;

    "...Of course bad things happen, and the resultant value at that memory location becomes incorrect." When you say it is incorrect, do you mean it is a random number which is different than either C5510's number or C6455's number? Or it is one of the DSPS' (C5510/C6455) number, but it is not the one you intend to write into?

    Wen

    Regards;

  • 0
    TI__Expert 6995 points

    Derek,

     

    You need to come up with a semaphore condition. Semaphores are the tools for multiprocessor systems to share resources.

    Reserve a memory location on the C55x. This will hold the value of the semaphore. When set, the shared buffer is locked and in use. When cleared, the shared buffer is unlocked and can be accessed by the C6455 or the C5510. When the C6455 writes to the C5510 memory, it needs to read the reserved memory location. If set, it needs to wait until clear before proceeding with the write. If cleared, it will set it and proceed with the access. SImilarly, when the C5510 accesses this shared buffer, it also needs to see if it is set before using the shared buffer. Depending on how you have constructed your two systems together, you could use DSP BIOS built in semaphores, an ISR to handle the semaphore (the C6455 HPI's interrupt and a software interrupt for the C5510), or multi-level semaphore to handle the read, test, and modify of the value in the semaphore.You want to make sure that when you read, test, and write the semaphore, the other processor does not interrupt this process.

     

    Hope this helps!

  • 0 in reply to PedroGelabert
    Expert 1215 points

    This sounds like a very useful method by which to proceed.  While I've managed to remove the possibility of simultaneous writes by using HWI_disable/HWI_restore, I may end up going your route if it looks like I'll need to suspend use of HWI_disable.  Thanks for the help, Pedro!