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RTOS/AM4377: SBL source code question

shigehiro tsuda
Mastermind 9490 points
Part Number: AM4377


Tool/software: TI-RTOS

Hi,

The following sources are probably wrong, are they correct?
When checking TRM of AM 437x, EMIF4D_IODFT_TEST_LOGIC_GLOBAL_CTRL Register is a register of EMIF module.

pdk_am437x_1_0_7\packages\ti\starterware\bootloader\src\am43xx\sbl_am437xx_platform_ddr.c

SblPlatformDdrConfig( )

......

if(SBL_PLATFORM_MEM_TYPE_DDR3 == memType)
{
/* hwlvmod reset applied after DDR PHY & IO control settings. */
HW_WR_REG32((SOC_CONTROL_MODULE_REG + EMIF_IODFT_TLGC), 0x00002011U);
HW_WR_REG32((SOC_CONTROL_MODULE_REG + EMIF_IODFT_TLGC), 0x00002411U);
HW_WR_REG32((SOC_CONTROL_MODULE_REG + EMIF_IODFT_TLGC), 0x00002011U);

/* Configure DDR I/O and Control module registers complete. */
HW_WR_REG32((SOC_EMIF_ADDRSP0_REG + EMIF_SDRAM_REF_CTRL), 0x80003000U);

regVal = pDdrEmifCfg->ddrPhyCtrl;
HW_WR_REG32((SOC_EMIF_ADDRSP0_REG + EMIF_DDR_PHY_CTRL_1), regVal);
HW_WR_REG32((SOC_EMIF_ADDRSP0_REG + EMIF_DDR_PHY_CTRL_1_SHDW), regVal);

/* Setting up DDR3 H/W levelling configuration. */
SblPlatformDdrPhyInit(&pDdrCfg->ddrEmifPhyCfg, memType);

/* hwlvmod reset applied after DDR PHY & IO control settings. */
HW_WR_REG32((SOC_CONTROL_MODULE_REG + EMIF_IODFT_TLGC), 0x00002011U);
HW_WR_REG32((SOC_CONTROL_MODULE_REG + EMIF_IODFT_TLGC), 0x00002411U);
HW_WR_REG32((SOC_CONTROL_MODULE_REG + EMIF_IODFT_TLGC), 0x00002011U);
}

....


"SOC_CONTROL_MODULE_REG + EMIF_IODFT_TLGC" seems to be a mistake of "SOC_EMIF_ADDRSP0_REG + EMIF_IODFT_TLGC".

Best Regards,
Shigehiro Tsuda

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0
    TI__Guru** 116770 points
    Tsuada-san,

    This appears to be a bug in the SBL DDR init code as you indicated. We have verified this by comparing it to the GEL initialization code and have filed a bug for the development team to track and fix in the code. Please use bug ID PRSDK-3311 for tracking this issue in the release notes.

    We may not be able to get this in the 4Q2017 as we are in code freeze for this release pending critical bugs so this may likely be fixed in 1Q2018.
    I will post on this thread if there is any change in plan.

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    Mastermind 9490 points

    Hi Rahul,

    Thank you for quick reply.
    I understood that it is bug.

    In addition, is also bug below?

    / * Finished with EMIF config. Set init bit back to enable. *

    HW_WR_REG 32 ((SOC_EMIF_ADDRSP 0 _REG + EMIF_SDRAM_REF_CTRL), 0x00003000 U);

    With DDR3 specifications, CKE must be held low for more than 500 μs from RESET release.

    The setting of 0x3000 when DDR3 clock is used at 400MHz is about 480us.
    u-boot seems to set this to 0x3100.
    For this setting, it will be over 500 μs.

    Best Regards,
    Shigehiro Tsuda

     

  • 0 in reply to shigehiro tsuda
    TI__Guru** 116770 points
    Tsuda-san,

    I have added to this to the same bug to be tracked. We will align the RTOS bootloader with the uboot but this should be considered non-critical as we have not had any issues reported from this issue.

    Regards,
    Rahul