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EPWMSYNCI pulse width

TM
Prodigy 40 points

Hello,

I'm working with a C6748, and am trying to determine the minimum pulse width for EPWMSYNCI, and/or a definition of "SCO" in terms of system clocking.

According to SPRS586A (section 6.28.1, p. 240), the sync input pulse width for the ePWM periperhal is 2* tc(SCO), or 2 * the SCO cycle time. 

I had assumed SCO = sysclkout, but a pulse width of that duration did not trigger the sync event (though much longer pulses did).

Any help appreciated.

  • 0
    TI__Expert 8785 points

    SCO should be equal to the frequency of SYSCLK2.  How long was the pulse width when it did not trigger?  How much did you need to increase the pulse width before it will work?

    --Christina

  • 0 in reply to clam
    Prodigy 40 points

     

    I started with a 1usec pulse which I assumed would be way more than enough as my SYSCLK2 is 150MHz.  I had to move it out to several usec (currently using five) for sync to work.    Are there any other electrical requirements that need to be met for that input?  Also, do the TBCTL CLKDIV divider values factor in somehow?

    thanks

     

  • 0 in reply to TM
    TI__Expert 8785 points

    I'm following up with some additional experts about the minimum required timing for the EPWMSYNCI pulse width.  In the mean time, can you let me know what frequency the TBCLK is running at, or your TBCTL CLKDIV values?

    --Christina

  • 0 in reply to clam
    Prodigy 40 points

    CLKDIV is set to divide by 4

    HSPCLKDIV is set to divide by 4

     

     

  • 0 in reply to TM
    TI__Expert 8785 points

    I've followed up with some additional experts.  They said that it should only require 2 (sysclk2) cycle time for the SYNCI pulse to get triggered.

    How are you generating and measuring the sync pulse?  Also, what method are you using to check if the sync pulse is getting triggered?

    --Christina

  • 0 in reply to clam
    Prodigy 40 points

    Thank you for looking into this further.

    At the moment, I'm driving a GPIO pin (a test setup; the reason for my query is to ensure the final hardware configuration drives the signal long enough).

    I have the PWM & GPIO pin output on a scope; when the sync does not occur as the waveform drifts all over the place - also it is evident the value in TBPHS is not being loaded.

    I verified this by setting the GPIO pulse wide enough to effect a SYNC, then disconnected/reconnected the GPIO to SYNCI - the change is very clear.