Hi
As you know we can swap data pins in the same byte lane.
Below is the pin assignment of J6P EVM, we can see it swaps some DQ pins on EMIF1 for better layout.
Is there any suggestion like this for two 96-Ball FBGA DDR3L on each EMIF?
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Hi
As you know we can swap data pins in the same byte lane.
Below is the pin assignment of J6P EVM, we can see it swaps some DQ pins on EMIF1 for better layout.
Is there any suggestion like this for two 96-Ball FBGA DDR3L on each EMIF?