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DRA712: DRA712 DDR3 layout guidelines

one and zero
Mastermind 18166 points
Part Number: DRA712

Dear Champs,

I didn't find an explicit statement about the DDR3 Clock to Address and Control signals or Data signals.
However since clock is in the net class of Address and Control signals I assume the Table 7-34 in the datasheet of DRA712 is all that needs to be respected. So max skew between clock and address control signals would be 29ns (CARS32) in case only one DDR3 memory is attached. Please confirm.

I'm a bit confused about CARS31 and CARS315 in table 7-34 which should specify the max. trace length.
For CARS31 it's 500ps for CARS315 it's 1020ps. I assume CARS31 is Manhattan distance and CARS315 is the 'real' distance. However the note A. says: 'Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils. The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.'
So what's the maximum length I should use for DDR3 CLK and Address control lines? Is it the 1020ps or the 500ps + 300 mils?

Thanks and regards,

one and zero

  • 0
    TI__Intellectual 1245 points

    Hi one and zero,

    The note A you are referring is valid for the maximum of 4 device used. And your case seems to be for a single device used, so you should stick to CARS31/32.

    Thanks,
    Dian

  • 0
    TI__Guru 52545 points

    Table 7-33 confirms the ADDR_CTRL is associated with the CK clock net class.  Yes - Table 7-34 requirements do cover CK net.  Just to confirm, CARS32 is 29ps, not 29ns as you stated.

    CARS31 (A1 + A2 net length) is max net length to first memory device.  A3, A4 would be nets to follow-on memory devices (if applicable).  Figure 7-62 might help clarify terms of A1, A2, A3, etc.

    CARS315 would be to max length of to all memory devices and termination (i.e max total length of the net).