CCS/TMDSLCDK138: McASP audio loopback example TDM configuration

Eloy Soto92

Part Number: TMDSLCDK138
Other Parts Discussed in Thread: TLV320AIC3106

Tool/software: Code Composer Studio

Hi,

I'm new to DSP development, and I'm using the StarterWare McASP Loopback example. I want to configure TDM time division to have the TLV320AIC3106 codec transmitting on different time slots (In a future, we will have 8 codecs connected to the same bus). In the given example, I'm changing the following code (8Khz, 160 samples):

/* Sampling Rate which will be used by both transmit and receive sections */
#define SAMPLING_RATE (8000u)

/* Number of samples to be used per audio buffer */
#define NUM_SAMPLES_PER_AUDIO_BUF (160u)

With this changes it's ok, audio loopback is working. To activate TDM on audio codec, I've change the file aic31.c to use 256-clock transmissions (function AIC31DataConfig):

Original code:

/* Write the data type and slot width */
CodecRegWrite(baseAddr, AIC31_P0_REG9, (dataType | slot));

Modified code (added 256-clock bit activation on P0 REG9):

/* Write the data type and slot width */
CodecRegWrite(baseAddr, AIC31_P0_REG9, (dataType | slot | 0x08));

On main file, I've changed the following code:

On AIC31I2SConfigure function (we will have 8 codecs, sampling R&L channels, so 16 slots per TMD frame, and I want the codec to transmit on slots 2&3, not 0&1 as originally, so I've changed the offset to start on bit 32):

    /* Configure the data format and sampling rate */
    //Original code: AIC31DataConfig(SOC_I2C_0_REGS, AIC31_DATATYPE_I2S, SLOT_SIZE, 0);
    AIC31DataConfig(SOC_I2C_0_REGS, AIC31_DATATYPE_I2S, SLOT_SIZE, 32);

On "" function, I've changed the McASP configuration to use 16 slots and to be active on slot 2&3 (not 0&1 as originally):

/* Configure the frame sync. I2S shall work in TDM format with 2 slots */
    //Original code: McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_RX_FS_WIDTH_WORD,
    //                    MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
    //McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 2, MCASP_TX_FS_WIDTH_WORD,
    //                    MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);

   // Configure 16 slots
    McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 16, MCASP_RX_FS_WIDTH_WORD,
                        MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
    McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 16, MCASP_TX_FS_WIDTH_WORD,
                        MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);

/* Enable the transmitter/receiver slots. I2S uses 2 slots */
//Original code: McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);
//McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, I2S_SLOTS);

//Set slots 2&3 as active on McASP serializers
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, 0x000000C);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, 0x0000000C);

I don't know what I'm missing on the configuration because it's not working, so any help will be welcome (I've tried with other transmissions formats such as left-justified or DSP and the result is the same).

Regards,

Eloy

over 8 years ago

0 Cvetolin Shulev-XID over 8 years ago

TI__Guru 65405 points

Hi Eloy,

Our team will need some time to gather data in the lab. Please allow us a few days and we will get back to you.

BR
Tsvetolin Shulev

0 Eloy Soto92 over 8 years ago in reply to Cvetolin Shulev-XID

Prodigy 40 points

Hi Tsvetolin,

Sure, no problem. I've been working on the example. With an oscilloscope, I've seen that the audio codec is sending data, but no data is going back to the codec on the TX line.

I think one problem on my original post was that using a left-adjusted (LEFTJ or I2S) format, I supposed that L&R data were going to be sent together. But with an oscilloscope I've seen that it's not correct. On the WCLK, the "high" side sends the L audio, and on the "low" part R audio. So I suppose that I don't need 16 slots but 8 instead, so I've changed the codec to sent data on slot 2 using 16-bits offset, and McASP with 8 slots being active only on slot 2:

//Send data with 16-bits offset
AIC31DataConfig(SOC_I2C_0_REGS, AIC31_DATATYPE_I2S, SLOT_SIZE, 16);

// Configure 8 slots
McASPRxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 8, MCASP_RX_FS_WIDTH_WORD,
MCASP_RX_FS_EXT_BEGIN_ON_FALL_EDGE);
McASPTxFrameSyncCfg(SOC_MCASP_0_CTRL_REGS, 8, MCASP_TX_FS_WIDTH_WORD,
MCASP_TX_FS_EXT_BEGIN_ON_RIS_EDGE);

//Set slot 2 as active on McASP serializers
McASPRxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, 0x0000002);
McASPTxTimeSlotSet(SOC_MCASP_0_CTRL_REGS, 0x00000002);

Another problem I've seen is that on I2SDataTxRxActivate function, the line "while(McASPTxStatusGet(SOC_MCASP_0_CTRL_REGS) & MCASP_TX_STAT_DATAREADY);" must not be executed when the codec is not transmitting on SLOT0, so for my tests I've commented it out.
Using watchpoints/breakpoints, I've seen that incomming data is copied from the RX buffers to the TX buffers on the main while loop:

/* Copy the buffer */
memcpy((void *)txBufPtr[lastSentTxBuf],
(void *)rxBufPtr[lastFullRxBuf],
AUDIO_BUF_SIZE);

It seems that it's valid data because values are changing (I've not decoded it :D ), but using breakpoints I can see that on the ISR code (function "EDMA3CCComplIsr"), the event for data Rx is happening, but the code for Tx complete event inside "EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS) & (1 << EDMA3_CHA_MCASP0_TX)" section is never executed.

Best regards,
Eloy

0 Sahin Okur over 8 years ago in reply to Eloy Soto92

TI__Mastermind 27355 points

Hello Eloy,

Please refer to the following documents for guidance on initialization and configuration:

Here are a couple of E2E posts that will hopefully point you in the right direction as well:

Please note that Starterware is legacy software that we can no longer support. The current supported software is Processor SDK: http://www.ti.com/tool/PROCESSOR-SDK-C6748

Hope this helps.

Best,

Sahin

0 Eloy Soto92 over 8 years ago in reply to Sahin Okur

Prodigy 40 points

Hi,

Thanks for the references, I've already see them. Now I'm in a point where if I use DSP mode on audio codec, EDMA transfers, and if I configure the McASP peripheral to use 8 slots of 32 bits, the frequency of DMA copies is also increased by 8.

I've configured the DMA to copy an entire frame (8 slots of 32 bits, 256 bits). If I set the McASP to work using 1 Slot all is fine, but if I increase it to 8 slots, the DMA is sending the Rx complete event 8 times faster, any idea why is this happening? Frame sync signal and bit clock as received from audio codec.

Best regards,
Eloy

0 Eloy Soto92 over 8 years ago in reply to Eloy Soto92

Prodigy 40 points

Answering to my last post, it's correct to have the RX complete event from DMA 8 times faster, as I'm configuring 8 slots per frame. What I'm seeing is that if I configure the codec in 256-clock mode, transmitting on first slot in DSP mode with both R&L channels (16 bits per channel), and McASP is configured to use 1 slot all is fine, but with 8 slots data is shifted on the frame. With an oscilloscope (channel 1 is Frame Sync signal, channel 3 is the codec output data) configuring one slot as shown in next image, data is sent correctly:

But if I activate 8 slots on McASP, the data is not equal, and it seems to be shifted on the frame:

One question is if the McASP is synchronized with frame sync signal. I think the problem could be that when I activate 8 slots, the RBUF is sending events to DMA, and the first received event could be from a "random slot", not the first one, and so the audio samples are shifted on the frame. It could be possible?

Another question is about the McASP XTDM and RTDM masks. Configured value is 0x000000FF for both, in order to receive/transmit on 8 slots (of 32 bits). I'm not sure if this is correct. On McASP manual, the XTDM register definition says that the value is "modulus 32" (which is not specified on RTDM register definition).

Best regards,

Eloy

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CCS/TMDSLCDK138: McASP audio loopback example TDM configuration