Hi
We are using the Sitara AM3359 processor. The processor is connected to an external SDRAM chip. In order to allow a cached and a not cached access to the SDRAM, the SDRAM controller is configured to the double size of the memory of the SDRAM chip. The highest address bit is not connected to the chip and therefore, the highest bit is not used to build the access address to the chip. With this configuration the lower half of the configured address space contains the same content as the higher half of the configured address space. The MMU is configured to cache the lower have of the configured address space. Access to the higher addresses is not cached.
The memory test (galpat) uses the not cached higher addresses to test the memory. In order to prevent memory manipulation during the test, the interrupts are closed when the test is executed.
Unfortunately, even with closed interrupts the test detects memory manipulations during its execution. Our first thought was DMA, however, no DMA is used to access addresses in the tested address space. The next thought was that the cache writes out some lines during the test. In order to prevent this, we ensured that the tested addresses are written back to RAM (cleaned) after the interrupts are closed but before the test starts. With this, the occurrence of manipulations during the test decreases. However, the manipulations still happen. With the write back (clean) of the tested addresses in the cache, it still happens about once in 24 hours.
We use the function CP15DCacheCleanBuff(tStartAddress_p, u32Size_p) to clean the tested address. The function is in the TI library.
Our question is, does the write back (clean) guarantee that all flushed lines are written to the SDRAM memory? What about any existing cache write buffers?
In the tests described above, the cache strategy was write back:
MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_ WB_WA, MMU_CACHE_WB_WA)
We also tried the cache strategy write through for the inner cache pool:
MMU_MEMTYPE_NORMAL_NON_SHAREABLE(MMU_CACHE_WT_NOWA, MMU_CACHE_WB_WA)
This seems to solve the problem with the unwanted memory access during the test execution. We are not sure why this solves the problem. Does it deactivate the write buffer of the cache? Does the write buffer cause our problems?
Is there a document, which describes the cache and its write buffers for the AM3359 processor?
Thank you for your answers.
