Linux/AM3352: NAND boot reset issue

Robert Yin17

Part Number: AM3352
Other Parts Discussed in Thread: TPS65910

Tool/software: Linux

AM3352 Nand Flash Boot Reset Issue

Hello,

We have a custom board which boots well and works fine(Linux command prompt could be entered) when SYSBOOT is 10111(MMC0 first).
Nand flash works ok when we use nand erase/write commands to write MLO and u-boot.img in U-Boot(BCH16 is used).

But when we change SYSBOOT to 10011(NAND first), board can not boot(blank screen on debug console).
The waveform is as below figure(PINs: PORZ, WARMRST/RESETIN_OUT, GPMC_CS0 for NAND, v3.3 for system power). It seems CPU reset frequently when SYSBOOT is 10011.

Related PINs figures(RTC_PWRONRST drawing is wrong, RTC_PWRONRST is connected to v1.8):

Details specs:
CPU: AM3352BZCZA100 (1GMhz)
PMIC: TI TPS65910A31A1RSLT
NAND: Micron MT29F2G08ABAGAWP
DDR3: MICRON MT41K512M16HA-107
Processor SDK: 2.00.02.11

We don't know why SD Card boots fine but NAND boot failed.
Any suggestion is appreciated. Thanks.

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

Hi,

What is the actual high level of SYS_PORZ? 1.35V is the absolute minimum for this signal.

0 Robert Yin17 over 8 years ago in reply to Biser Gatchev-XID

Prodigy 160 points

Hi Biser

PORZ pin is connected to VRTC(which is 1.8 v) of TPS65910.
Thanks.

0 Biser Gatchev-XID over 8 years ago in reply to Robert Yin17

TI__Guru**** 393215 points

Please post the schematic. If you have connected PORZ to VRTC this is absolutely wrong.

0 Robert Yin17 over 8 years ago in reply to Biser Gatchev-XID

Prodigy 160 points

Hi Biser,

HW guy said VRTC(1.8V ) could meeting the min. requirement( 1.35V) of PORZ. Is this correct ?

Schematic will be provided later.

0 Robert Yin17 over 8 years ago in reply to Robert Yin17

Prodigy 160 points

Hi Biser,

Schematic is attached. Thank you.

0 Biser Gatchev-XID over 8 years ago in reply to Robert Yin17

TI__Guru**** 393215 points

OK, this seems fine. Where is RTC_PORZ connected? It must not be left unconnected.

0 Robert Yin17 over 8 years ago in reply to Biser Gatchev-XID

Prodigy 160 points

Hi Biser,

RTC_PORZ is as below figure:

+V1.8_RTC_Out is from PMIC.

Thanks.

0 Biser Gatchev-XID over 8 years ago in reply to Robert Yin17

TI__Guru**** 393215 points

It's not a good idea to connect an RC circuit directly to the reset input, as the rise time is too slow and may cause problems, but that's aside from the issue. Another thing you should check is whether the main oscillator is at full swing and stable at reset release time. Also check whether the NAND doesn't require some delay before it's initially accessed.

0 Robert Yin17 over 8 years ago in reply to Biser Gatchev-XID

Prodigy 160 points

Hi Biser,

Is there any issue that may cause CPU reset frequently ?
Thanks.

0 Biser Gatchev-XID over 8 years ago in reply to Robert Yin17

TI__Guru**** 393215 points

When no valid boot device is found the internal watchdog will reset the processor.

0 Robert Yin17 over 8 years ago in reply to Biser Gatchev-XID

Prodigy 160 points

Hi Biser,

So you mean CPU may not find Nand flash and internal watchdog triggers reset?
But it is strange that waveform shows CS0 is activated.
Thanks.

0 Biser Gatchev-XID over 8 years ago in reply to Robert Yin17

TI__Guru**** 393215 points

CS0 is activated, because the NAND boot sequence starts. However if the NAND doesn't respond nothing will happen. Where is the R/B signal from the NAND connected? It must be on GPMC_WAIT0 with external pullup resistor.

0 Biser Gatchev-XID over 8 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

Is this resolved? If it is, please mark as "Resolved" so we can close the thread.

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Linux/AM3352: NAND boot reset issue