L138 DDR Timing Analysis tool

tehoaislimau

Is there a timing analysis tool already available that allows uses to test how much timing margin the board design has on the DDR bus?

This is to specifically test timing marginallities caused by implementation, layout and or different memory vendors.

over 15 years ago

0 jc-ti over 15 years ago

TI__Mastermind 27585 points

There are tools available to do this but the IBIS models we provide cannot be used for timing simulation for the DDR interface.

The timings are guaranteed by following the layout rules in the datasheet. As long as the memory is JEDEC compliant, boards following the datasheet rules will work at full speed.

Jeff

0 parvin sherakar over 14 years ago in reply to jc-ti

Prodigy 10 points

Hi,

Please let me know about the tool with which we can perform timing analysis for OMAP and external memories interface, OMAP and FPGA interfdace.

-Parvin

0 jc-ti over 14 years ago in reply to parvin sherakar

TI__Mastermind 27585 points

Hi Parvin,

As I mentioned before, we do not provide the timing data to do DDR timing analysis. Operation is guaranteed by following the routing rules found in the datasheet.

Jeff

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L138 DDR Timing Analysis tool