Example code, posts on the E2E forums, and my testing all indicate that IPCGR1 and the related registers are covered by the "boot kicker" protection scheme. Thus, any core that wants to perform IPC must unlock the boot kicker before writing to those registers, write to those registers, and perhaps re-lock the boot kicker. [UPDATE:] My testing also shows that the locking state is shared between cores; for example, core 0 can unlock the kicker, core 1 can write to the BOOTCFG space, and core 1 can then lock the kicker, making core 0 unable to write to BOOTCFG until someone unlocks the kicker again.
Is the preferred solution to this race condition to keep the kicker unlocked, to use some external serialization mechanism (such as the hardware semaphore module), to just not use the IPCGRx registers for IPC (e.g. using Multicore Navigator instead), or something else? SPRS691E (the data sheet for the C6678) says to leave the kicker unlocked, but SPRS689D (the data sheet for the C6670) says to lock it after each access.
