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DM6441 8 bit NAND boot failure

Edmund Pirali
Intellectual 495 points

I am having an issue booting from a supported Micron Device on the DM6441. This is on our own board (not EVM). I am able to correctly flash the NAND with a small test code (have read through the bootloader, write the correct ECC for device at correct position, etc). The problem is this: the bootloader fails to boot and when I check the ACR for CS2 it is attempting to access the EMIF space as a 16 bit device, although EM_WIDTH from the BOOTCFG shows correctly that the buss width should be 8 bits. In fact if I manually change the A1CR to 8 bit and specific values, reset the DSP from CCS and run the bootloader will load and run the code correctly (so it is definitely not a flashing or code issue).

After the failed boot the BOOTCFG read 0x112 (EM_WIDTH 0, BTSEL 00 NAND, 64x self boot), but the A1CR reads 0x0050043D, which is 16 bit NAND access). If I change the A1CR to 0x1FFFFFFC (8 bit), Reset the CPU and hit run then the code is loaded and runs properly.

So it looks like the bootloader is somehow NOT respecting EM_WIDTH when it sets up A1CR. Am I missing anything?

  • 0
    Intellectual 495 points

    Never mind, I was confusing myself. It appears to be a problem with the code (depends on GEL set up, obvious error). But I got thrown by NOT realizing the Gel also overwrites the A1CR for 16 bit NOR.

    So off to working on the code itself.

  • 0 in reply to Edmund Pirali
    Intellectual 495 points

    Alright, got the setting up power domain, PLL, etc into the boot code and now have a different issue. IF I power cycle the device it will NOT read from NAND (and fails to boot, when connecting with no GEL the PC is in the ROM bootloader). But if I then Reset the CPU from CCS and hit run it will load and run the code properly.

    Again, all the bootcfg settings are correct. Thoughts?

  • 0 in reply to Edmund Pirali
    Intellectual 495 points

    Well, one more step (just posting here in case anyone runs into this). We were letting the DSP boot itself (DSP_BT=1), which interferes with the ROM bootloader. I am guessing it maybe because it in the shadow of the EMIFA CS2 and interferes with the ECC calculations performed by the bootloader, making it think the NAND is not valid.

    But anyway, if the DSP_BT is set to 0 then all is well.