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TCI6630K2L: usage of L2 cache for program (.text section)

Rao Besthamalla
Prodigy 225 points

Part Number: TCI6630K2L

Hi 

Due to design constraints, I am running my program (.text section) from DDR3 using L1P cache.

But this comes at a penalty due to DDR3 access. To improve the system performance,  in addition to L1P cache, I wanted to use L2 cache also .

But when L2 cache is enabled (32/64/256 KB) with appropriate changes in the repository file and by enabling L2 cache (using appropriate APIs in the application), the system behavior is modified.

I confirmed this observation several times. In this context, I have couple of questions.

- Is it possible to run the program from DDR3 memory via L1P and L2 caches ?

- if so, would there be any performance benefit using both types cache memories?

- Are there any other changes required in the project to use L2 cache for accessing program code ?

- Is there any example project depicting the usage L2 cache for program code access ?

Do let me know if you need any other details for answering my queries. I sincerely appreciate your help in advance.

I am using following binaries.

MCSDK 3.1.3.6

SYS/BIOS 6.41.0.26

Best Regards

Rao