Hello, I wanted to make sure I understand the boot process so I have summarized what I think I know and need an understanding check. If not please advise how to fix it or include a bit more detail for me.
AFTER POWER SEQUENCE HAS COMPLETED:
- BOOT MODE STRAPPING PINS SETTINGS LATCHED ON RISING EDGE OF RESET ARE STORED INTO DEVSTAT REGISTER (BOOTMODE[15:0] pins map to DEVSTAT[16:1] bits)
-ARM COREPAC0 IS DETERMINED AS THE BOOT MASTER AND SPI PORT 1 IS BOOT PORT USING CHIP SELECT 0
-ARM COREPAC0 BEGINS EXECUTING FROM EMBEDDED BOOT ROM
-ARM COREPAC0 READS USER BOOT UP PROGRAM FROM SPI SERIAL PORT 1 AND STORES TO MSMC
-ARM COREPAC0 EXECUTES THE BOOTUP CODE (FROM MSMC) WHICH INITIALIZES THE EXTERNAL DDR3L MEMORY DEVICES
-ARM COREPAC0 THEN COPIES (REALLOCATES)THE MSMC USER BOOT CODE INTO EXTERNAL DDR3L
-ARMCOREPAC0 CONTINUES EXECUTING THE USER BOOT CODE FROM DDR3L WHICH READS ALL CORE’S APPLICATION PROGRAM AND DATA FROM SPI FLASH AND STORES INTO SPECIFIED GP HEADER ADDRESS MEMORY SPACE (LOCAL OR GLOBAL)
-ARMCOREPAC0 INITIATES ARMCOREPAC1 AND DSPCOREPAC 0-3 AS NEEDED USING THE IPC REGISTERS
-ALL CORES INITIATED WILL BEGIN THEIR EXECUTION AT THE MEMORY LOCATION INDICATED BY THE MASTER CORE