Hi,
we need some clarification on the SDRAM_REF_CTRL register bit 31 reg_initref_dis.
Q1: The TRM states in Table 7-223 that this bit has RESET value of 1. Is this correct?
A customer sees that this bit is set to 0, on coming out of chip reset ...
Do to this we are concerned that earlier DDR initialization sequences may have started.
Q2: When reg_initref_dis is set to 1, are there any possibilities to initiate a DDR3 initialization sequence, or is this bit completely protecting from having an initialization start?
Q3: Specifically if reg_initref_dis is set to 1, does a write to the SDRAM_CONFIG register cause an initialization to start?
Thanks,
--Gunter
