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66AK2L06: DDR3 ram access with 66AK2L06

Thomas Schoen
Prodigy 20 points
Part Number: 66AK2L06

Hello,

we are currently evaluating the use of 66AK2L06 as an upgrad for our backend platform.
From the datasheet (page 4) it seems that the external DDR3 Ram cannot be accessed directly from all the processing units (i.e. ARM A15, C66x, FFTC, etc.), but needs to be transfered through the 2MB MSM/SRAM. Is my understanding of the Block Diagramm correct?

In our application, we will sample approx. 192 MB via JESD to the DDR3 ram and want to apply different data processing steps on the data with difference cores at different times. Therefore, all processing units need to have access to the data in the DDR3 ram via DMA. Is that possible?

We appreciate your help.

Regards,

Tom

  • 0
    TI__Mastermind 21025 points
    Hi Tom,

    Sorry for the delay. Yes, DDR is available to all cores and peripherals. It would be good to map out the data flow from reception to the various memories and peripherals you will need to use. Because there are multiple DMA domains (primarily Multicore Navigator and EDMA) the effects of DDR latency can often be eliminated because the DMAs can prefetch data either to peripheral memory or to a lower latency RAM in the background.

    An example of this is having a Navigator loop that copies DDR descriptors (chunks of memory) to L2 descriptors while a peripheral is consuming the L2 descriptors that have already been copied.

    It is also typical that the ARM cores use a virtual mapping of memory while the DSP cores use physical addresses. Multicore Navigator does require the use of physical addresses, which requires address conversion in the QMSS LLD drivers.