Other Parts Discussed in Thread: SYSBIOS,
Please let me know about the implementation of "User RAM" (addresses 0x0F80 - 0x0FFF of the registers space in Sitara Ethercat Slave Controller. I have not found anything in the documents.
Thank you
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There are a couple of ways to see how memory is used. The project will create a map file. For a default installation of the full featured EtherCAT build it will be :C:\ti\PRU-ICSS-EtherCAT_Slave_01.00.04.02\protocols\ethercat_slave\projects\ethercat_slave_full_AM335x_arm\AM335x_release\ethercat_slave_full_AM335x_arm.map
I find this sometimes hard to use.
My preferred method is to copy the out file that is in the same directory: C:\ti\PRU-ICSS-EtherCAT_Slave_01.00.04.02\protocols\ethercat_slave\projects\ethercat_slave_full_AM335x_arm\AM335x_release\ethercat_slave_full_AM335x_arm.out into a temporary directory.
The I create a DOS window and CD to that directory. In the dos window I apply
C:\ti\gcc-arm-none-eabi-4_9-2015q3\bin\arm-none-eabi-objdump.exe -x -w ethercat_slave_full_AM335x_arm.out > ethercat_slave_full_AM335x_arm.txt
This creates a text file which contains a summary of the memory regions and a symbol table.
If I import the text file into excel as a space delimited file where all of the contents are imported as text items (to preserve the HEX values). I then usually copy the symbol table to a separate sheet so that I can reformat it and sort it.
The summary table looks like:
Sections: | ||||||||||||
Idx | Name | Size in Decmal | Size | VMA | LMA | File | off | Algn | Flags | |||
0 | .c_int00 | 180 | 000000b4 | 80000000 | 80000000 | 00008000 | 2**2 | CONTENTS, | ALLOC, | LOAD, | READONLY, | CODE |
1 | ti.sysbios.family.arm.a8.mmuTableSection | 16384 | 00004000 | 80004000 | 80004000 | 000080b4 | 2**14 | ALLOC | ||||
2 | xdc.meta | 311 | 00000137 | 80008000 | 80008000 | 00034058 | 2**2 | CONTENTS, | READONLY | |||
3 | .text | 146132 | 00023ad4 | 80008140 | 80008140 | 00008140 | 2**4 | CONTENTS, | ALLOC, | LOAD, | READONLY, | CODE |
4 | .rodata | 26004 | 00006594 | 8002bc18 | 8002bc18 | 0002bc18 | 2**3 | CONTENTS, | ALLOC, | LOAD, | READONLY, | DATA |
5 | .vectors | 64 | 00000040 | 80032400 | 80032400 | 00032400 | 2**10 | CONTENTS, | ALLOC, | LOAD, | READONLY, | DATA |
6 | .ARM.exidx | 8 | 00000008 | 80032440 | 80032440 | 00032440 | 2**2 | CONTENTS, | ALLOC, | LOAD, | READONLY, | DATA |
7 | .data | 7184 | 00001c10 | 80032448 | 80032448 | 00032448 | 2**3 | CONTENTS, | ALLOC, | LOAD, | DATA | |
8 | .bss | 60408 | 0000ebf8 | 80034058 | 80034058 | 00034058 | 2**3 | ALLOC | ||||
9 | .stack | 16384 | 00004000 | 80042c50 | 80042c50 | 00034058 | 2**3 | ALLOC | ||||
10 | .comment | 00000150 | 00000000 | 00000000 | 0003418f | 2**0 | CONTENTS, | READONLY | ||||
11 | .ARM.attributes | 0000003d | 00000000 | 00000000 | 000342df | 2**0 | CONTENTS, | READONLY | ||||
12 | .debug_aranges | 00003990 | 00000000 | 00000000 | 00034320 | 2**3 | CONTENTS, | READONLY, | DEBUGGING | |||
13 | .debug_info | 0007a9c8 | 00000000 | 00000000 | 00037cb0 | 2**0 | CONTENTS, | READONLY, | DEBUGGING | |||
14 | .debug_abbrev | 0000fa1b | 00000000 | 00000000 | 000b2678 | 2**0 | CONTENTS, | READONLY, | DEBUGGING | |||
15 | .debug_line | 00024a8d | 00000000 | 00000000 | 000c2093 | 2**0 | CONTENTS, | READONLY, | DEBUGGING | |||
16 | .debug_frame | 00008b48 | 00000000 | 00000000 | 000e6b20 | 2**2 | CONTENTS, | READONLY, | DEBUGGING | |||
17 | .debug_str | 00035498 | 00000000 | 00000000 | 000ef668 | 2**0 | CONTENTS, | READONLY, | DEBUGGING | |||
18 | .debug_loc | 00027e01 | 00000000 | 00000000 | 00124b00 | 2**0 | CONTENTS, | READONLY, | DEBUGGING | |||
19 | .debug_ranges | 00004230 | 00000000 | 00000000 | 0014c908 | 2**3 | CONTENTS, | READONLY, | DEBUGGING |
The Symbol table for the memory regions you are interested in is:
SYMBOL | TABLE: | |||||
Hex Add | Decimal Size | Hex Size | Symbol | |||
00000001 | l | *ABS* | 0 | 00000000 | xdc_runtime_Startup__EXECFXN__C | |
00000001 | l | *ABS* | 0 | 00000000 | xdc_runtime_Startup__RESETFXN__C | |
00000004 | l | *ABS* | 0 | 00000000 | ARG1 | |
00000040 | l | *ABS* | 0 | 00000000 | Cache_sizeL1dCacheLine | |
00000040 | l | *ABS* | 0 | 00000000 | Cache_sizeL1pCacheLine | |
00000040 | l | *ABS* | 0 | 00000000 | Cache_sizeL2CacheLine | |
00000400 | l | *ABS* | 0 | 00000000 | HEAPSIZE | |
00004000 | g | *ABS* | 0 | 00000000 | __STACK_SIZE | |
00004000 | g | *ABS* | 0 | 00000000 | __TI_STACK_SIZE | |
0001c000 | l | *ABS* | 0 | 00000000 | STACKSIZE | |
48200000 | g | *ABS* | 0 | 00000000 | ti_sysbios_family_arm_a8_intcps_Hwi_intc | |
80000000 | l | d | .c_int00 | 0 | 00000000 | .c_int00 |
80000000 | g | .c_int00 | 0 | 00000000 | _c_int00 | |
8000009c | l | .c_int00 | 0 | 00000000 | _reset_fxns_done_ | |
80004000 | l | d | ti.sysbios.family.arm.a8.mmuTableSection | 0 | 00000000 | ti.sysbios.family.arm.a8.mmuTableSection |
80004000 | g | O | ti.sysbios.family.arm.a8.mmuTableSection | 16384 | 00004000 | ti_sysbios_family_arm_a8_Mmu_Module_State_0_tableBuf__A |
David
Sorry, I'll try to explain better, my question is referred to to the implementation of TI ESC that runs into the PRU-ICSS of AM3359 and emulates Beckhoff ET1100 with some exceptions. Inside the document "EtherCAT_firmware_API_Guide.pdf" there is a chapter "AM335x EtherCAT Register List" where the ESC registers, visible both to ESC and Ethercat Master, are listed with a column dedicated to "Register offset", but no information about the interval between 0x0F80 and 0x 0FFF, that is named "User ram" in Bechoff ET1100 datasheet. Neither reports anything about. I need to know if the registers in the 0x0F80 - 0x 0FFF interval or a portion of this are implemented.
Thank in advance
Lamberto