Other Parts Discussed in Thread: SYSBIOS
Tool/software: TI-RTOS
Hello,
We are sharing data among cores which are defined in the MSMC memory. To avoid having problem with data coherency and to avoid using cache functions (wb, wbInv, inv), we have defined a section in the MSMC which is remapped to address 0xA1000000. We then disable the cache for this section with corresponding MAR register. However it doesn't work for the core that load the data in memory (core0). Here are some screenshots showing the problem.
As you can see, the shared data at address 0xA1xxxxxx are cached (in green). The corresponding MAR register (MAR 161) is configured properly. The MPAX is also configured properly because the shared data are initialized variable and it would crash during startup (in _auto_init_elf function called in _c_int00() ) if MPAX was wrong.
Here is the platform definition:
In my C6678.cmd file, the MSMCRAM_CACHE and MSMCRAM_NO_CACHE sections are only loaded by Core0:
/* Shared code and data */
.sharedCode > MSMCSRAM_CACHE
.sharedVar > MSMCSRAM_NO_CACHE
And other cores includes the .obj file where these data are defined but without loading them:
/* Shared code and data */
.sharedCode > MSMCSRAM_CACHE, type = NOLOAD
.sharedVar > MSMCSRAM_NO_CACHE, type = NOLOAD
The data coherency is good for all other cores but Core0. Data from Core0 are not seen by other cores and data from other cores are not seen by Core0.
We are using sysbios 6.46.05.55, xdc tool 3.32.1.22
Any idea how to make this work?
Thanks
Hugo
