AM5728: DDR3 clock invert setting

shigehiro tsuda

Part Number: AM5728

Hi,

When DDR3 HW leveling is used, is it necessary to set the following registers depending on the trace length of CLK and DQS?

EMIF_DDR_PHY_CONTROL_1[18] .PHY_INVERT_CLKOUT
EMIF_EXT_PHY_CONTROL_1[19:10] .PHY_REG_CTRL_SLAVE_RATIO1
EMIF_EXT_PHY_CONTROL_1[9:0] .PHY_REG_CTRL_SLAVE_RATIO0

Is this setting effective only when software leveling is used?

Best Regards,
Shigehiro Tsuda

over 7 years ago

0 Biser Gatchev-XID over 7 years ago

TI__Guru**** 393215 points

The DDR experts have been notified. They will respond here.

0 sivak over 7 years ago in reply to Biser Gatchev-XID

TI__Genius 9655 points

Tsuda-san

Please use the AM57x EMIF tool to review the right settings. The link is here - www.ti.com/.../sprac36

With regard to your question, there is no need to configure the tool for this setting. The tool always sets EMIF_DDR_PHY_CONTROL_1[18] .PHY_INVERT_CLKOUT = 0x1 and therefore, EMIF_EXT_PHY_CONTROL_1[19:10] .PHY_REG_CTRL_SLAVE_RATIO1
EMIF_EXT_PHY_CONTROL_1[9:0] .PHY_REG_CTRL_SLAVE_RATIO0 will be set to 0x100

Regards, Siva

0 shigehiro tsuda over 7 years ago in reply to sivak

Mastermind 9490 points

Hi Siva,

Thank you for quick reply.

I understand that phy_invert_clock_out will always be 0x1 if the value calculated by the AM572x EMIF tool is used.

Which register reflects the information entered in step2 of the AM572x EMIF tool?

Best Regards,
Shigehiro Tsuda

0 sivak over 7 years ago in reply to shigehiro tsuda

TI__Genius 9655 points

Tsuda-san

Step2 information is not required while using HW leveling. It is only required for SW leveling which is not recommended for AM57x. Please let me know if you have any other questions.

Regards, Siva

0 shigehiro tsuda over 7 years ago in reply to sivak

Mastermind 9490 points

Hi Siva,

Thank you for the reply.
When using HW leveling, I understand that it is not necessary to set Step 2.

Our customer is creating new boards.
Once the DDR3 evaluation begins, I may ask you again.
I look forward to your support at that time.

Best Regards,
Shigehiro Tsuda

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AM5728: DDR3 clock invert setting